| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_dccg.c | 46 void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
88 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg21_update_dpp_dto()
93 DPPCLK_DTO_ENABLE[dpp_inst], 1); in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
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| D | dcn21_dccg.h | 35 void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dccg.c | 47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
64 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg2_update_dpp_dto()
68 DPPCLK_DTO_ENABLE[dpp_inst], 1); in dccg2_update_dpp_dto()
71 DPPCLK_DTO_ENABLE[dpp_inst], 0); in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
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| D | dcn20_hwseq.h | 94 unsigned int dpp_inst,
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| D | dcn20_dccg.h | 217 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
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| D | dcn20_hwseq.c | 418 unsigned int dpp_inst, in dcn20_dpp_pg_control() argument
429 switch (dpp_inst) { in dcn20_dpp_pg_control()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_hwseq.c | 45 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) in dcn302_dpp_pg_control() argument
55 switch (dpp_inst) { in dcn302_dpp_pg_control()
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| D | dcn302_hwseq.h | 31 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_hwseq.h | 13 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
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| D | dcn303_hwseq.c | 27 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) in dcn303_dpp_pg_control() argument
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dccg.h | 70 int dpp_inst,
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dmub_psr.c | 283 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_psr_copy_settings()
285 copy_settings_data->dpp_inst = 0; in dmub_psr_copy_settings()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 110 int dpp_inst, dppclk_khz, prev_dppclk_khz; in dcn20_update_clocks_update_dpp_dto() local
115 dpp_inst = i; in dcn20_update_clocks_update_dpp_dto()
122 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer_private.h | 116 unsigned int dpp_inst,
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 109 int dpp_inst, dppclk_khz, prev_dppclk_khz; in rn_update_clocks_update_dpp_dto() local
114 dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst; in rn_update_clocks_update_dpp_dto()
121 clk_mgr->dccg, dpp_inst, dppclk_khz); in rn_update_clocks_update_dpp_dto()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.h | 92 unsigned int dpp_inst,
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| D | dcn10_hw_sequencer.c | 555 unsigned int dpp_inst, in dcn10_dpp_pg_control() argument
566 switch (dpp_inst) { in dcn10_dpp_pg_control()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dmub/inc/ |
| D | dmub_cmd.h | 1337 uint8_t dpp_inst; member
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