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Searched refs:dpm_table (Results 1 – 21 of 21) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega12_hwmgr.c602 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega12_setup_single_dpm_table() argument
612 dpm_table->count = num_of_levels; in vega12_setup_single_dpm_table()
619 dpm_table->dpm_levels[i].value = clk; in vega12_setup_single_dpm_table()
620 dpm_table->dpm_levels[i].enabled = true; in vega12_setup_single_dpm_table()
639 struct vega12_single_dpm_table *dpm_table; in vega12_setup_default_dpm_tables() local
642 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); in vega12_setup_default_dpm_tables()
645 dpm_table = &(data->dpm_table.soc_table); in vega12_setup_default_dpm_tables()
647 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); in vega12_setup_default_dpm_tables()
652 dpm_table->count = 1; in vega12_setup_default_dpm_tables()
653 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; in vega12_setup_default_dpm_tables()
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Dvega20_hwmgr.c559 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega20_setup_single_dpm_table() argument
569 dpm_table->count = num_of_levels; in vega20_setup_single_dpm_table()
576 dpm_table->dpm_levels[i].value = clk; in vega20_setup_single_dpm_table()
577 dpm_table->dpm_levels[i].enabled = true; in vega20_setup_single_dpm_table()
587 struct vega20_single_dpm_table *dpm_table; in vega20_setup_gfxclk_dpm_table() local
590 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_gfxclk_dpm_table()
592 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); in vega20_setup_gfxclk_dpm_table()
597 dpm_table->count = 1; in vega20_setup_gfxclk_dpm_table()
598 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; in vega20_setup_gfxclk_dpm_table()
608 struct vega20_single_dpm_table *dpm_table; in vega20_setup_memclk_dpm_table() local
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Dvega10_hwmgr.c1231 struct vega10_single_dpm_table *dpm_table, in vega10_setup_default_single_dpm_table() argument
1236 dpm_table->count = 0; in vega10_setup_default_single_dpm_table()
1239 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= in vega10_setup_default_single_dpm_table()
1241 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_single_dpm_table()
1243 dpm_table->dpm_levels[dpm_table->count].enabled = true; in vega10_setup_default_single_dpm_table()
1244 dpm_table->count++; in vega10_setup_default_single_dpm_table()
1251 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); in vega10_setup_default_pcie_table()
1302 struct vega10_single_dpm_table *dpm_table; in vega10_setup_default_dpm_tables() local
1344 dpm_table = &(data->dpm_table.soc_table); in vega10_setup_default_dpm_tables()
1346 dpm_table, in vega10_setup_default_dpm_tables()
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Dsmu7_hwmgr.c663 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, in smu7_setup_default_pcie_table()
674 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, in smu7_setup_default_pcie_table()
680 data->dpm_table.pcie_speed_table.count = max_entry - 1; in smu7_setup_default_pcie_table()
684 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, in smu7_setup_default_pcie_table()
689 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, in smu7_setup_default_pcie_table()
694 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, in smu7_setup_default_pcie_table()
699 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, in smu7_setup_default_pcie_table()
704 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, in smu7_setup_default_pcie_table()
709 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, in smu7_setup_default_pcie_table()
715 data->dpm_table.pcie_speed_table.count = 6; in smu7_setup_default_pcie_table()
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Dsmu_helper.c351 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_reset_single_dpm_table() local
353 dpm_table->count = count > max ? max : count; in phm_reset_single_dpm_table()
355 for (i = 0; i < dpm_table->count; i++) in phm_reset_single_dpm_table()
356 dpm_table->dpm_level[i].enabled = false; in phm_reset_single_dpm_table()
366 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_setup_pcie_table_entry() local
367 dpm_table->dpm_level[index].value = pcie_gen; in phm_setup_pcie_table_entry()
368 dpm_table->dpm_level[index].param1 = pcie_lanes; in phm_setup_pcie_table_entry()
369 dpm_table->dpm_level[index].enabled = 1; in phm_setup_pcie_table_entry()
376 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_get_dpm_level_enable_mask_value() local
378 for (i = dpm_table->count; i > 0; i--) { in phm_get_dpm_level_enable_mask_value()
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Dsmu7_hwmgr.h214 struct smu7_dpm_table dpm_table; member
Dvega12_hwmgr.h314 struct vega12_dpm_table dpm_table; member
Dvega10_hwmgr.h311 struct vega10_dpm_table dpm_table; member
Dvega20_hwmgr.h437 struct vega20_dpm_table dpm_table; member
/Linux-v5.15/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dnavi10_ppt.c982 struct smu_11_0_dpm_table *dpm_table; in navi10_set_default_dpm_table() local
986 dpm_table = &dpm_context->dpm_tables.soc_table; in navi10_set_default_dpm_table()
990 dpm_table); in navi10_set_default_dpm_table()
993 dpm_table->is_fine_grained = in navi10_set_default_dpm_table()
996 dpm_table->count = 1; in navi10_set_default_dpm_table()
997 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in navi10_set_default_dpm_table()
998 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
999 dpm_table->min = dpm_table->dpm_levels[0].value; in navi10_set_default_dpm_table()
1000 dpm_table->max = dpm_table->dpm_levels[0].value; in navi10_set_default_dpm_table()
1004 dpm_table = &dpm_context->dpm_tables.gfx_table; in navi10_set_default_dpm_table()
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Dsienna_cichlid_ppt.c671 struct smu_11_0_dpm_table *dpm_table; in sienna_cichlid_set_default_dpm_table() local
677 dpm_table = &dpm_context->dpm_tables.soc_table; in sienna_cichlid_set_default_dpm_table()
682 dpm_table); in sienna_cichlid_set_default_dpm_table()
685 dpm_table->is_fine_grained = in sienna_cichlid_set_default_dpm_table()
688 dpm_table->count = 1; in sienna_cichlid_set_default_dpm_table()
689 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in sienna_cichlid_set_default_dpm_table()
690 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
691 dpm_table->min = dpm_table->dpm_levels[0].value; in sienna_cichlid_set_default_dpm_table()
692 dpm_table->max = dpm_table->dpm_levels[0].value; in sienna_cichlid_set_default_dpm_table()
696 dpm_table = &dpm_context->dpm_tables.gfx_table; in sienna_cichlid_set_default_dpm_table()
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Darcturus_ppt.c343 struct smu_11_0_dpm_table *dpm_table = NULL; in arcturus_set_default_dpm_table() local
347 dpm_table = &dpm_context->dpm_tables.soc_table; in arcturus_set_default_dpm_table()
351 dpm_table); in arcturus_set_default_dpm_table()
354 dpm_table->is_fine_grained = in arcturus_set_default_dpm_table()
357 dpm_table->count = 1; in arcturus_set_default_dpm_table()
358 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in arcturus_set_default_dpm_table()
359 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
360 dpm_table->min = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
361 dpm_table->max = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
365 dpm_table = &dpm_context->dpm_tables.gfx_table; in arcturus_set_default_dpm_table()
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/Linux-v5.15/drivers/gpu/drm/amd/pm/swsmu/smu13/
Daldebaran_ppt.c294 struct smu_13_0_dpm_table *dpm_table = NULL; in aldebaran_set_default_dpm_table() local
299 dpm_table = &dpm_context->dpm_tables.soc_table; in aldebaran_set_default_dpm_table()
303 dpm_table); in aldebaran_set_default_dpm_table()
307 dpm_table->count = 1; in aldebaran_set_default_dpm_table()
308 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in aldebaran_set_default_dpm_table()
309 dpm_table->dpm_levels[0].enabled = true; in aldebaran_set_default_dpm_table()
310 dpm_table->min = dpm_table->dpm_levels[0].value; in aldebaran_set_default_dpm_table()
311 dpm_table->max = dpm_table->dpm_levels[0].value; in aldebaran_set_default_dpm_table()
315 dpm_table = &dpm_context->dpm_tables.gfx_table; in aldebaran_set_default_dpm_table()
318 dpm_table->count = 2; in aldebaran_set_default_dpm_table()
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/Linux-v5.15/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dfiji_smumgr.c490 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table() local
502 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
504 dpm_table->TargetTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
511 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); in fiji_populate_bapm_parameters_in_dpm_table()
512 dpm_table->GpuTjHyst = 8; in fiji_populate_bapm_parameters_in_dpm_table()
514 dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase; in fiji_populate_bapm_parameters_in_dpm_table()
517 dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
519 dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
521 dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
523 dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
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Diceland_smumgr.c767 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_smc_link_level() local
772 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in iceland_populate_smc_link_level()
774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
788 (uint8_t)dpm_table->pcie_speed_table.count; in iceland_populate_smc_link_level()
790 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in iceland_populate_smc_link_level()
963 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_all_graphic_levels() local
980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
996 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
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Dci_smumgr.c475 struct smu7_dpm_table *dpm_table = &data->dpm_table; in ci_populate_all_graphic_levels() local
485 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
487 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
493 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
500 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
502 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
719 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in ci_populate_bapm_parameters_in_dpm_table() local
725 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
726 dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
728 dpm_table->DTETjOffset = 0; in ci_populate_bapm_parameters_in_dpm_table()
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Dvegam_smumgr.c575 struct smu7_dpm_table *dpm_table = &data->dpm_table; in vegam_populate_smc_link_level() local
580 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in vegam_populate_smc_link_level()
582 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in vegam_populate_smc_link_level()
584 dpm_table->pcie_speed_table.dpm_levels[i].param1); in vegam_populate_smc_link_level()
592 (uint8_t)dpm_table->pcie_speed_table.count; in vegam_populate_smc_link_level()
596 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in vegam_populate_smc_link_level()
869 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in vegam_populate_all_graphic_levels() local
873 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in vegam_populate_all_graphic_levels()
889 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
892 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
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Dtonga_smumgr.c510 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_smc_link_level() local
515 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in tonga_populate_smc_link_level()
517 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in tonga_populate_smc_link_level()
519 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level()
531 (uint8_t)dpm_table->pcie_speed_table.count; in tonga_populate_smc_link_level()
533 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in tonga_populate_smc_link_level()
691 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_all_graphic_levels() local
693 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; in tonga_populate_all_graphic_levels()
710 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
712 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
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Dpolaris10_smumgr.c820 struct smu7_dpm_table *dpm_table = &data->dpm_table; in polaris10_populate_smc_link_level() local
825 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in polaris10_populate_smc_link_level()
827 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level()
829 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level()
837 (uint8_t)dpm_table->pcie_speed_table.count; in polaris10_populate_smc_link_level()
841 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in polaris10_populate_smc_link_level()
1040 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in polaris10_populate_all_graphic_levels() local
1044 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in polaris10_populate_all_graphic_levels()
1067 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1070 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
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/Linux-v5.15/drivers/gpu/drm/radeon/
Dci_dpm.c411 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
419 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
420 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
422 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
423 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
425 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
427 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
430 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
431 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
433 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
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Dci_dpm.h195 struct ci_dpm_table dpm_table; member