| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dccg.h | 58 struct dccg { struct
69 void (*update_dpp_dto)(struct dccg *dccg, argument
72 void (*get_dccg_ref_freq)(struct dccg *dccg,
75 void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
77 void (*otg_add_pixel)(struct dccg *dccg,
79 void (*otg_drop_pixel)(struct dccg *dccg,
81 void (*dccg_init)(struct dccg *dccg);
84 struct dccg *dccg,
90 struct dccg *dccg,
97 struct dccg *dccg,
[all …]
|
| D | clk_mgr.h | 285 struct dccg;
287 …clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);
|
| D | clk_mgr_internal.h | 220 struct dccg *dccg; member
|
| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto()
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq() argument
81 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_get_dccg_ref_freq()
[all …]
|
| D | dcn20_dccg.h | 211 struct dccg base;
217 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
219 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
223 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
225 void dccg2_otg_add_pixel(struct dccg *dccg,
227 void dccg2_otg_drop_pixel(struct dccg *dccg,
231 void dccg2_init(struct dccg *dccg);
233 struct dccg *dccg2_create(
239 void dcn_dccg_destroy(struct dccg **dccg);
|
| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
46 struct dccg *dccg, in dccg31_set_physymclk() argument
51 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_set_physymclk()
113 struct dccg *dccg, in dccg31_set_dtbclk_dto() argument
119 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_set_dtbclk_dto()
142 if (dccg->ref_dtbclk_khz && req_dtbclk_khz) { in dccg31_set_dtbclk_dto()
146 modulo = dccg->ref_dtbclk_khz * 1000; in dccg31_set_dtbclk_dto()
147 phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + dccg->ref_dtbclk_khz - 1), in dccg31_set_dtbclk_dto()
[all …]
|
| D | dcn31_dccg.h | 125 struct dccg *dccg31_create(
131 void dccg31_init(struct dccg *dccg);
134 struct dccg *dccg,
140 struct dccg *dccg,
144 struct dccg *dccg,
|
| D | dcn31_hwseq.c | 106 if (res_pool->dccg->funcs->dccg_init) in dcn31_init_hw()
107 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn31_init_hw()
132 if (res_pool->dccg && res_pool->hubbub) { in dcn31_init_hw()
134 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn31_init_hw()
|
| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
46 void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto()
50 if (dccg->ref_dppclk) { in dccg21_update_dpp_dto()
51 int ref_dppclk = dccg->ref_dppclk; in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
109 struct dccg *dccg21_create( in dccg21_create()
116 struct dccg *base; in dccg21_create()
|
| D | dcn21_dccg.h | 29 struct dccg *dccg21_create(
35 void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
|
| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 108 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
118 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn20_update_clocks_update_dpp_dto()
121 clk_mgr->dccg->funcs->update_dpp_dto( in dcn20_update_clocks_update_dpp_dto()
122 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
146 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
159 dccg->funcs->set_fifo_errdet_ovr_en( in dcn20_update_clocks_update_dentist()
160 dccg, in dcn20_update_clocks_update_dentist()
163 dccg->funcs->otg_drop_pixel( in dcn20_update_clocks_update_dentist()
164 dccg, in dcn20_update_clocks_update_dentist()
166 dccg->funcs->set_fifo_errdet_ovr_en( in dcn20_update_clocks_update_dentist()
[all …]
|
| D | dcn20_clk_mgr.h | 29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
|
| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
55 struct dccg *dccg3_create( in dccg3_create()
62 struct dccg *base; in dccg3_create()
80 struct dccg *dccg30_create( in dccg30_create()
87 struct dccg *base; in dccg30_create()
|
| D | dcn30_dccg.h | 69 struct dccg *dccg3_create(
75 struct dccg *dccg30_create(
|
| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
54 struct dccg *dccg301_create( in dccg301_create()
61 struct dccg *base; in dccg301_create()
|
| D | dcn301_dccg.h | 53 struct dccg *dccg301_create(
59 struct dccg *dccg301_create(
|
| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| D | clk_mgr.c | 135 … clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create() argument
221 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
226 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
248 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
252 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
256 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
259 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
270 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
285 dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
|
| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.h | 39 struct dccg *dccg);
|
| D | rn_clk_mgr.c | 106 clk_mgr->dccg->ref_dppclk = ref_dpp_clk; in rn_update_clocks_update_dpp_dto()
117 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in rn_update_clocks_update_dpp_dto()
120 clk_mgr->dccg->funcs->update_dpp_dto( in rn_update_clocks_update_dpp_dto()
121 clk_mgr->dccg, dpp_inst, dppclk_khz); in rn_update_clocks_update_dpp_dto()
931 struct dccg *dccg) in rn_clk_mgr_construct() argument
947 clk_mgr->dccg = dccg; in rn_clk_mgr_construct()
|
| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.h | 34 struct dccg *dccg);
|
| D | dcn30_clk_mgr.c | 533 struct dccg *dccg) in dcn3_clk_mgr_construct() argument
541 clk_mgr->dccg = dccg; in dcn3_clk_mgr_construct()
|
| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.h | 45 struct dccg *dccg);
|
| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.h | 45 struct dccg *dccg);
|
| D | dcn31_clk_mgr.c | 627 struct dccg *dccg) in dcn31_clk_mgr_construct() argument
636 clk_mgr->base.dccg = dccg; in dcn31_clk_mgr_construct()
693 clk_mgr->base.dccg->ref_dtbclk_khz = 600000; in dcn31_clk_mgr_construct()
|
| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| D | dce_clk_mgr.h | 48 int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);
|
