| /Linux-v5.15/drivers/crypto/qat/qat_common/ |
| D | adf_gen4_hw_data.h | 27 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
28 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
31 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
32 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
35 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
36 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
38 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
39 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
42 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
44 void __iomem *_csr_base_addr = csr_base_addr; \
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| D | adf_gen2_hw_data.h | 28 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
29 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
31 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
32 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
34 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
35 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
37 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
38 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
40 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
45 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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| D | adf_gen4_hw_data.c | 11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
35 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
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| D | adf_gen2_hw_data.c | 63 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
65 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
68 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
71 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
74 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
76 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
79 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
82 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
85 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
87 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
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| D | adf_accel_devices.h | 115 u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
117 void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
119 u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
121 void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
123 u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
124 void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
126 void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
128 void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
130 void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
131 void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
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