Searched refs:clk_pll1 (Results 1 – 4 of 4) sorted by relevance
71 static struct clk clk_pll1 = { variable75 .parent = &clk_pll1,78 .parent = &clk_pll1,81 .parent = &clk_pll1,214 INIT_CK(NULL, "pll1", &clk_pll1),367 max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4); in calc_clk_div()383 mclk = &clk_pll1; in calc_clk_div()549 clk_pll1.rate = clk_xtali.rate; in ep93xx_clock_init()551 clk_pll1.rate = calc_pll_rate(value); in ep93xx_clock_init()554 clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; in ep93xx_clock_init()[all …]
735 phy->clk_pll1 = of_clk_get_by_name(node, "pll-1"); in sun8i_hdmi_phy_probe()736 if (IS_ERR(phy->clk_pll1)) { in sun8i_hdmi_phy_probe()738 ret = PTR_ERR(phy->clk_pll1); in sun8i_hdmi_phy_probe()756 clk_put(phy->clk_pll1); in sun8i_hdmi_phy_probe()774 clk_put(phy->clk_pll1); in sun8i_hdmi_phy_remove()
155 parents[1] = __clk_get_name(phy->clk_pll1); in sun8i_phy_clk_create()
171 struct clk *clk_pll1; member
