| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 160 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) in dcn3_init_clocks() argument
162 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_init_clocks()
165 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn3_init_clocks()
166 clk_mgr_base->clks.p_state_change_support = true; in dcn3_init_clocks()
167 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn3_init_clocks()
170 if (!clk_mgr_base->bw_params) in dcn3_init_clocks()
173 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) in dcn3_init_clocks()
185 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
190 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
195 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn3_init_clocks()
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| D | dcn30_clk_mgr.h | 29 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 207 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, in dcn2_update_clocks() argument
211 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn2_update_clocks()
213 struct dc *dc = clk_mgr_base->ctx->dc; in dcn2_update_clocks()
220 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
228 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
233 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn2_update_clocks()
253 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
254 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
256 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
260 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks()
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| D | dcn20_clk_mgr.h | 56 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 92 void rn_set_low_power_state(struct clk_mgr *clk_mgr_base) in rn_set_low_power_state() argument
94 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rn_set_low_power_state()
98 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_set_low_power_state()
126 void rn_update_clocks(struct clk_mgr *clk_mgr_base, in rn_update_clocks() argument
130 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rn_update_clocks()
132 struct dc *dc = clk_mgr_base->ctx->dc; in rn_update_clocks()
138 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in rn_update_clocks()
149 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_update_clocks()
156 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_update_clocks()
161 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in rn_update_clocks()
[all …]
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 102 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable) in dcn31_disable_otg_wa() argument
104 struct dc *dc = clk_mgr_base->ctx->dc; in dcn31_disable_otg_wa()
121 static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, in dcn31_update_clocks() argument
126 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn31_update_clocks()
128 struct dc *dc = clk_mgr_base->ctx->dc; in dcn31_update_clocks()
143 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { in dcn31_update_clocks()
145 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn31_update_clocks()
148 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn31_update_clocks()
150 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn31_update_clocks()
153 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn31_update_clocks()
[all …]
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 190 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, in rv1_update_clocks() argument
194 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rv1_update_clocks()
195 struct dc *dc = clk_mgr_base->ctx->dc; in rv1_update_clocks()
227 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz in rv1_update_clocks()
228 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz in rv1_update_clocks()
229 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz in rv1_update_clocks()
230 || new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz) in rv1_update_clocks()
233 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { in rv1_update_clocks()
234 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in rv1_update_clocks()
242 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { in rv1_update_clocks()
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| D | rv1_clk_mgr_clk.c | 52 …egisters(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk_mgr *clk_mgr_base) in rv1_dump_clk_registers() argument
54 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rv1_dump_clk_registers()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
| D | dce120_clk_mgr.c | 84 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, in dce12_update_clocks() argument
88 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_update_clocks()
97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce12_update_clocks()
107 clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk); in dce12_update_clocks()
109 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); in dce12_update_clocks()
112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks()
115 clk_mgr_base->clks.phyclk_khz = max_pix_clk; in dce12_update_clocks()
117 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); in dce12_update_clocks()
119 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce12_update_clocks()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
| D | dce112_clk_mgr.c | 70 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) in dce112_set_clock() argument
72 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_set_clock()
74 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; in dce112_set_clock()
75 struct dc *dc = clk_mgr_base->ctx->dc; in dce112_set_clock()
104 if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) && in dce112_set_clock()
105 ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))) in dce112_set_clock()
195 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base, in dce112_update_clocks() argument
199 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_update_clocks()
207 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce112_update_clocks()
211 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce112_update_clocks()
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| D | dce112_clk_mgr.h | 35 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/ |
| D | dce60_clk_mgr.c | 83 static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce60_get_dp_ref_freq_khz() argument
85 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_get_dp_ref_freq_khz()
120 static void dce60_update_clocks(struct clk_mgr *clk_mgr_base, in dce60_update_clocks() argument
124 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_update_clocks()
132 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce60_update_clocks()
136 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce60_update_clocks()
140 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce60_update_clocks()
141 patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce60_update_clocks()
142 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce60_update_clocks()
144 dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce60_update_clocks()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| D | dce_clk_mgr.c | 129 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce_get_dp_ref_freq_khz() argument
131 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_dp_ref_freq_khz()
155 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce12_get_dp_ref_freq_khz() argument
157 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_get_dp_ref_freq_khz()
159 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz); in dce12_get_dp_ref_freq_khz()
195 struct clk_mgr *clk_mgr_base, in dce_get_required_clocks_state() argument
198 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_required_clocks_state()
230 struct clk_mgr *clk_mgr_base, in dce_set_clock() argument
233 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_set_clock()
235 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; in dce_set_clock()
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| D | dce_clk_mgr.h | 34 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
36 struct clk_mgr *clk_mgr_base,
51 struct clk_mgr *clk_mgr_base,
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.c | 92 void vg_update_clocks(struct clk_mgr *clk_mgr_base, in vg_update_clocks() argument
96 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in vg_update_clocks()
98 struct dc *dc = clk_mgr_base->ctx->dc; in vg_update_clocks()
113 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in vg_update_clocks()
125 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in vg_update_clocks()
130 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in vg_update_clocks()
135 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in vg_update_clocks()
139 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc-… in vg_update_clocks()
140 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in vg_update_clocks()
141 dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); in vg_update_clocks()
[all …]
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| D | clk_mgr.c | 300 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) in dc_destroy_clk_mgr() argument
302 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dc_destroy_clk_mgr()
305 switch (clk_mgr_base->ctx->asic_id.chip_family) { in dc_destroy_clk_mgr()
307 if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
310 if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
313 if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
319 if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev)) in dc_destroy_clk_mgr()
324 if (ASICREV_IS_YELLOW_CARP(clk_mgr_base->ctx->asic_id.hw_internal_rev)) in dc_destroy_clk_mgr()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| D | dce110_clk_mgr.c | 249 static void dce11_update_clocks(struct clk_mgr *clk_mgr_base, in dce11_update_clocks() argument
253 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce11_update_clocks()
261 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce11_update_clocks()
265 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce11_update_clocks()
269 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
271 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce11_update_clocks()
273 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce11_update_clocks()
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