| /Linux-v5.15/drivers/clk/ti/ |
| D | clockdomain.c | 51 clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm()
57 __func__, clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm()
63 __func__, clk_hw_get_name(hw), clk->clkdm_name, ret); in omap2_clkops_enable_clkdm()
85 clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm()
91 __func__, clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm()
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| D | clkt_dflt.c | 114 idlest_val, clk_hw_get_name(&clk->hw)); in _omap2_module_wait_ready()
221 __func__, clk_hw_get_name(hw), in omap2_dflt_clk_enable()
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| D | dpll3xxx.c | 69 clk_name = clk_hw_get_name(&clk->hw); in _omap3_wait_dpll_status()
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
193 clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_bypass()
223 pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_stop()
538 __func__, clk_hw_get_name(hw), in omap3_noncore_dpll_enable()
675 clk_hw_get_name(hw), rate); in omap3_noncore_dpll_set_rate()
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| /Linux-v5.15/drivers/clk/ux500/ |
| D | clk-prcmu.c | 45 clk_hw_get_name(hw)); in clk_prcmu_unprepare()
103 (char *)clk_hw_get_name(hw), in clk_prcmu_opp_prepare()
107 __func__, clk_hw_get_name(hw)); in clk_prcmu_opp_prepare()
116 (char *)clk_hw_get_name(hw)); in clk_prcmu_opp_prepare()
131 clk_hw_get_name(hw)); in clk_prcmu_opp_unprepare()
137 (char *)clk_hw_get_name(hw)); in clk_prcmu_opp_unprepare()
153 __func__, clk_hw_get_name(hw)); in clk_prcmu_opp_volt_prepare()
176 clk_hw_get_name(hw)); in clk_prcmu_opp_volt_unprepare()
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| /Linux-v5.15/drivers/clk/zynqmp/ |
| D | pll.c | 53 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_get_mode()
76 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_mode()
139 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_recalc_rate()
183 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_rate()
229 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_is_enabled()
253 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_enable()
281 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_disable()
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| D | clk-gate-zynqmp.c | 37 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_enable()
57 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_disable()
77 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_is_enabled()
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| D | clk-mux-zynqmp.c | 46 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_mux_get_parent()
76 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_mux_set_parent()
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| D | divider.c | 83 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_recalc_rate()
169 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_round_rate()
226 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_set_rate()
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| /Linux-v5.15/drivers/clk/ |
| D | clk-xgene.c | 64 pr_debug("%s pll %s\n", clk_hw_get_name(hw), in xgene_clk_pll_is_enabled()
112 clk_hw_get_name(hw), fvco / nout, parent_rate, in xgene_clk_pll_recalc_rate()
453 pr_debug("%s clock enabled\n", clk_hw_get_name(hw)); in xgene_clk_enable()
461 clk_hw_get_name(hw), in xgene_clk_enable()
472 clk_hw_get_name(hw), in xgene_clk_enable()
493 pr_debug("%s clock disabled\n", clk_hw_get_name(hw)); in xgene_clk_disable()
519 pr_debug("%s clock checking\n", clk_hw_get_name(hw)); in xgene_clk_is_enabled()
522 pr_debug("%s clock is %s\n", clk_hw_get_name(hw), in xgene_clk_is_enabled()
545 clk_hw_get_name(hw), in xgene_clk_recalc_rate()
551 clk_hw_get_name(hw), parent_rate, parent_rate); in xgene_clk_recalc_rate()
[all …]
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| D | clk-versaclock5.c | 1012 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1028 parent_names[0] = clk_hw_get_name(&vc5->clk_mul); in vc5_probe()
1030 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1044 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd); in vc5_probe()
1063 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw); in vc5_probe()
1081 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1094 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw); in vc5_probe()
1096 parent_names[1] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1099 clk_hw_get_name(&vc5->clk_out[n - 1].hw); in vc5_probe()
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| D | clk-si5351.c | 438 __func__, clk_hw_get_name(hw), in si5351_pll_recalc_rate()
496 __func__, clk_hw_get_name(hw), a, b, c, in si5351_pll_round_rate()
525 __func__, clk_hw_get_name(hw), in si5351_pll_set_rate()
636 __func__, clk_hw_get_name(hw), in si5351_msynth_recalc_rate()
749 __func__, clk_hw_get_name(hw), a, b, c, divby4, in si5351_msynth_round_rate()
781 __func__, clk_hw_get_name(hw), in si5351_msynth_set_rate()
924 __func__, clk_hw_get_name(&drvdata->clkout[num].hw), in _si5351_clkout_reset_pll()
1082 __func__, clk_hw_get_name(hw), (1 << rdiv), in si5351_clkout_round_rate()
1133 __func__, clk_hw_get_name(hw), (1 << rdiv), in si5351_clkout_set_rate()
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| /Linux-v5.15/drivers/clk/sunxi-ng/ |
| D | ccu_frac.c | 67 pr_debug("%s: Read fractional\n", clk_hw_get_name(&common->hw)); in ccu_frac_helper_read_rate()
73 clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]); in ccu_frac_helper_read_rate()
78 clk_hw_get_name(&common->hw), reg, cf->select); in ccu_frac_helper_read_rate()
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| D | ccu_sdm.c | 114 clk_hw_get_name(&common->hw)); in ccu_sdm_helper_read_rate()
120 clk_hw_get_name(&common->hw)); in ccu_sdm_helper_read_rate()
125 clk_hw_get_name(&common->hw), reg); in ccu_sdm_helper_read_rate()
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| /Linux-v5.15/drivers/clk/qcom/ |
| D | clk-regmap-mux-div.c | 27 const char *name = clk_hw_get_name(&md->clkr.hw); in mux_div_set_src_div()
63 const char *name = clk_hw_get_name(&md->clkr.hw); in mux_div_get_src_div()
166 const char *name = clk_hw_get_name(hw); in mux_div_get_parent()
208 const char *name = clk_hw_get_name(hw); in mux_div_recalc_rate()
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| /Linux-v5.15/drivers/clk/berlin/ |
| D | berlin2-pll.c | 53 pr_warn("%s has zero rfdiv\n", clk_hw_get_name(hw)); in berlin2_pll_recalc_rate()
62 clk_hw_get_name(hw), vcodivsel); in berlin2_pll_recalc_rate()
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| /Linux-v5.15/drivers/clk/st/ |
| D | clkgen-fsyn.c | 342 clk_hw_get_name(hw), __func__); in quadfs_pll_fs660c32_recalc_rate()
390 __func__, clk_hw_get_name(hw), in quadfs_pll_fs660c32_round_rate()
415 __func__, clk_hw_get_name(hw), in quadfs_pll_fs660c32_set_rate()
573 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); in quadfs_fsynth_enable()
598 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); in quadfs_fsynth_disable()
615 __func__, clk_hw_get_name(hw), nsb); in quadfs_fsynth_is_enabled()
809 clk_hw_get_name(hw), __func__); in quadfs_recalc_rate()
812 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); in quadfs_recalc_rate()
825 __func__, clk_hw_get_name(hw), in quadfs_round_rate()
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| /Linux-v5.15/drivers/clk/imx/ |
| D | clk-scu.c | 246 clk_hw_get_name(hw), ret); in clk_scu_recalc_rate()
338 clk_hw_get_name(hw), ret); in clk_scu_get_parent()
366 clk_hw_get_name(hw), ret); in clk_scu_set_parent()
422 pr_warn("%s: clk unprepare failed %d\n", clk_hw_get_name(hw), in clk_scu_unprepare()
583 dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent), in imx_clk_scu_suspend()
608 clk_hw_get_name(clk->parent), in imx_clk_scu_resume()
799 pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw), in clk_gpr_gate_scu_unprepare()
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| /Linux-v5.15/drivers/clk/samsung/ |
| D | clk-pll.c | 111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); in samsung_pll_lock_wait()
259 drate, clk_hw_get_name(hw)); in samsung_pll35xx_set_rate()
368 drate, clk_hw_get_name(hw)); in samsung_pll36xx_set_rate()
481 drate, clk_hw_get_name(hw)); in samsung_pll45xx_set_rate()
618 drate, clk_hw_get_name(hw)); in samsung_pll46xx_set_rate()
823 drate, clk_hw_get_name(hw)); in samsung_s3c2410_pll_set_rate()
1019 drate, clk_hw_get_name(hw)); in samsung_pll2550xx_set_rate()
1114 drate, clk_hw_get_name(hw)); in samsung_pll2650x_set_rate()
1204 drate, clk_hw_get_name(hw)); in samsung_pll2650xx_set_rate()
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| /Linux-v5.15/drivers/clk/socfpga/ |
| D | clk-gate.c | 33 const char *name = clk_hw_get_name(hwclk); in socfpga_clk_get_parent()
59 const char *name = clk_hw_get_name(hwclk); in socfpga_clk_set_parent()
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| D | clk-gate-s10.c | 56 const char *name = clk_hw_get_name(hwclk); in socfpga_gate_get_parent()
86 const char *name = clk_hw_get_name(hwclk); in socfpga_agilex_gate_get_parent()
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| /Linux-v5.15/drivers/clk/nxp/ |
| D | clk-lpc32xx.c | 517 clk_hw_get_name(hw), in clk_pll_recalc_rate()
526 clk_hw_get_name(hw), in clk_pll_recalc_rate()
590 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate); in clk_hclk_pll_round_rate()
619 clk_hw_get_name(hw), rate); in clk_hclk_pll_round_rate()
637 clk_hw_get_name(hw), rate, m, n, p); in clk_hclk_pll_round_rate()
640 clk_hw_get_name(hw), rate, m, n, p, o); in clk_hclk_pll_round_rate()
652 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate); in clk_usb_pll_round_rate()
802 pr_debug("%s: 0x%x\n", clk_hw_get_name(hw), clk->enable); in clk_usb_enable()
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| /Linux-v5.15/drivers/clk/microchip/ |
| D | clk-core.c | 423 __func__, clk_hw_get_name(hw), req->rate); in roclk_determine_rate()
428 clk_hw_get_name(hw), req->rate, in roclk_determine_rate()
429 clk_hw_get_name(best_parent_clk), best_parent_rate, in roclk_determine_rate()
455 pr_err("%s: poll failed, clk active\n", clk_hw_get_name(hw)); in roclk_set_parent()
878 clk_hw_get_name(hw), nosc, cosc); in sclk_set_parent()
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| /Linux-v5.15/drivers/clk/rockchip/ |
| D | clk-pll.c | 411 clk_hw_get_name(hw)); in rockchip_rk3066_pll_recalc_rate()
490 __func__, clk_hw_get_name(hw), drate, prate); in rockchip_rk3066_pll_set_rate()
496 drate, clk_hw_get_name(hw)); in rockchip_rk3066_pll_set_rate()
551 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, in rockchip_rk3066_pll_init()
556 __func__, clk_hw_get_name(hw)); in rockchip_rk3066_pll_init()
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| D | clk-inverter.c | 44 __func__, degrees, clk_hw_get_name(hw)); in rockchip_inv_set_phase()
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| /Linux-v5.15/drivers/clk/baikal-t1/ |
| D | ccu-pll.c | 113 pr_err("Can't enable '%s' with no parent", clk_hw_get_name(hw)); in ccu_pll_enable()
127 pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw)); in ccu_pll_enable()
267 pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw)); in ccu_pll_set_rate_reset()
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