Searched refs:clk_div_mask (Results 1 – 7 of 7) sorted by relevance
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()55 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate()91 val &= ~(clk_div_mask(div->width) << div->shift); in clk_divider_gate_set_rate()137 val &= clk_div_mask(div->width); in clk_divider_disable()150 val &= clk_div_mask(div->width); in clk_divider_is_enabled()210 val &= clk_div_mask(width); in imx_clk_hw_divider_gate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()44 div_value &= clk_div_mask(PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()110 val &= ~((clk_div_mask(divider->width) << divider->shift) | in imx8m_clk_composite_divider_set_rate()111 (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); in imx8m_clk_composite_divider_set_rate()
48 unsigned int maxdiv = 0, mask = clk_div_mask(width); in _get_table_maxdiv()72 return clk_div_mask(width); in _get_maxdiv()74 return 1 << clk_div_mask(width); in _get_maxdiv()77 return clk_div_mask(width) + 1; in _get_maxdiv()99 return val ? val : clk_div_mask(width) + 1; in _get_div()124 return (div == clk_div_mask(width) + 1) ? 0 : div; in _get_val()156 val &= clk_div_mask(divider->width); in clk_divider_recalc_rate()438 val &= clk_div_mask(divider->width); in clk_divider_round_rate()459 val &= clk_div_mask(divider->width); in clk_divider_determine_rate()483 return min_t(unsigned int, value, clk_div_mask(width)); in divider_get_val()[all …]
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()399 val &= clk_div_mask(divider->width); in m10v_clk_divider_round_rate()430 val &= ~(clk_div_mask(divider->width) << divider->shift); in m10v_clk_divider_set_rate()
610 val &= clk_div_mask(div->width); in bm1880_clk_div_recalc_rate()630 val &= clk_div_mask(div->width); in bm1880_clk_div_round_rate()662 val &= ~(clk_div_mask(div->width) << div_hw->div.shift); in bm1880_clk_div_set_rate()
73 val &= clk_div_mask(div->width); in clk_regmap_div_recalc_rate()93 val &= clk_div_mask(div->width); in clk_regmap_div_determine_rate()118 clk_div_mask(div->width) << div->shift, val); in clk_regmap_div_set_rate()
606 #define clk_div_mask(width) ((1 << (width)) - 1) macro
