Searched refs:clk_csr (Results 1 – 15 of 15) sorted by relevance
46 int clk_csr; member
202 int clk_csr; member
118 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_read()186 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_write()241 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_read()310 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_write()
24 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()77 plat->clk_csr = 5; in snps_gmac5_default_data()
14 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in loongson_default_data()
301 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { in stmmac_clk_csr_set()303 priv->clk_csr = STMMAC_CSR_20_35M; in stmmac_clk_csr_set()305 priv->clk_csr = STMMAC_CSR_35_60M; in stmmac_clk_csr_set()307 priv->clk_csr = STMMAC_CSR_60_100M; in stmmac_clk_csr_set()309 priv->clk_csr = STMMAC_CSR_100_150M; in stmmac_clk_csr_set()311 priv->clk_csr = STMMAC_CSR_150_250M; in stmmac_clk_csr_set()313 priv->clk_csr = STMMAC_CSR_250_300M; in stmmac_clk_csr_set()318 priv->clk_csr = 0x03; in stmmac_clk_csr_set()320 priv->clk_csr = 0x02; in stmmac_clk_csr_set()322 priv->clk_csr = 0x01; in stmmac_clk_csr_set()[all …]
447 plat->clk_csr = -1; in stmmac_probe_config_dt()448 of_property_read_u32(np, "clk_csr", &plat->clk_csr); in stmmac_probe_config_dt()
231 int clk_csr; member
416 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()452 plat->clk_csr = 5; in intel_mgbe_common_data()
176 priv->clk_csr = SXGBE_CSR_100_150M; in sxgbe_clk_csr_set()178 priv->clk_csr = SXGBE_CSR_150_250M; in sxgbe_clk_csr_set()180 priv->clk_csr = SXGBE_CSR_250_300M; in sxgbe_clk_csr_set()182 priv->clk_csr = SXGBE_CSR_300_350M; in sxgbe_clk_csr_set()184 priv->clk_csr = SXGBE_CSR_350_400M; in sxgbe_clk_csr_set()186 priv->clk_csr = SXGBE_CSR_400_500M; in sxgbe_clk_csr_set()2160 if (!priv->plat->clk_csr) in sxgbe_drv_probe()2163 priv->clk_csr = priv->plat->clk_csr; in sxgbe_drv_probe()
48 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
489 int clk_csr; member
475 unsigned int clk_csr = handle->chip_info->glb_clk_enable_csr; in qat_hal_clr_reset() local494 csr_val = GET_CAP_CSR(handle, clk_csr); in qat_hal_clr_reset()496 SET_CAP_CSR(handle, clk_csr, csr_val); in qat_hal_clr_reset()
753 clk_csr = <0>;
370 int clk_csr;
