Searched refs:cb_color_bo_offset (Results 1 – 2 of 2) sorted by relevance
52 u64 cb_color_bo_offset[8]; member314 track->cb_color_bo_offset[i] = 0xFFFFFFFF; in r600_cs_track_init()380 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i]; in r600_cs_track_validate_cb()443 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { in r600_cs_track_validate_cb()454 track->cb_color_bo_offset[i], tmp, in r600_cs_track_validate_cb()1204 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp]; in r600_cs_check_reg()1235 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp]; in r600_cs_check_reg()1280 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
49 u32 cb_color_bo_offset[12]; member130 track->cb_color_bo_offset[i] = 0xFFFFFFFF; in evergreen_cs_track_init()436 offset = track->cb_color_bo_offset[id] << 8; in evergreen_cs_track_validate_cb()458 tmp = track->cb_color_bo_offset[id] << 8; in evergreen_cs_track_validate_cb()481 track->cb_color_bo_offset[id] << 8, mslice, in evergreen_cs_track_validate_cb()1561 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()1577 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
