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Searched refs:amdgpu_sriov_vf (Results 1 – 25 of 71) sorted by relevance

123

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dnv.c185 if (amdgpu_sriov_vf(adev)) { in nv_query_video_codecs()
721 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
723 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
732 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
742 if (!amdgpu_sriov_vf(adev)) { in nv_set_ip_blocks()
751 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
760 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
763 if (!amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
769 if (!amdgpu_sriov_vf(adev)) { in nv_set_ip_blocks()
781 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
[all …]
Damdgpu_virt.h250 #define amdgpu_sriov_vf(adev) \ macro
260 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
263 (amdgpu_sriov_vf((adev)) && \
267 (amdgpu_sriov_vf((adev)) && \
271 (amdgpu_sriov_vf((adev)) && \
275 (amdgpu_sriov_vf((adev)) && \
Dpsp_v11_0_8.c63 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_stop()
94 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_create()
176 if (amdgpu_sriov_vf(adev)) in psp_v11_0_8_ring_get_wptr()
188 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_set_wptr()
Dsoc15.c772 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
814 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
840 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
845 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
851 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { in soc15_set_ip_blocks()
865 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
877 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
887 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
893 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
899 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
[all …]
Damdgpu_psp.c72 if (amdgpu_sriov_vf(adev)) in psp_check_pmfw_centralized_cstate_management()
261 if (!amdgpu_sriov_vf(adev)) { in psp_sw_init()
267 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { in psp_sw_init()
459 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); in psp_cmd_submit_buf()
517 if (amdgpu_sriov_vf(psp->adev)) in psp_prep_tmr_cmd_buf()
579 if (!amdgpu_sriov_vf(psp->adev) && in psp_tmr_init()
590 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; in psp_tmr_init()
618 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) in psp_tmr_load()
638 if (amdgpu_sriov_vf(psp->adev)) in psp_prep_tmr_unload_cmd_buf()
671 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; in psp_tmr_terminate()
[all …]
Dpsp_v3_1.c229 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_create()
291 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
302 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
378 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_get_wptr()
389 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_set_wptr()
Dathub_v1_0.c68 if (amdgpu_sriov_vf(adev)) in athub_v1_0_set_clockgating()
93 if (amdgpu_sriov_vf(adev)) in athub_v1_0_get_clockgating()
Dpsp_v12_0.c265 if (amdgpu_sriov_vf(psp->adev)) { in psp_v12_0_ring_create()
317 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
328 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
395 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_get_wptr()
407 if (amdgpu_sriov_vf(adev)) { in psp_v12_0_ring_set_wptr()
Dmmhub_v1_0.c113 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_system_aperture_regs()
160 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_cache_regs()
211 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_disable_identity_aperture()
302 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_update_power_gating()
313 if (amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_enable()
359 if (!amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_disable()
378 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_fault_enable_default()
529 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_clockgating()
554 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_get_clockgating()
Damdgpu_vf_error.c36 if (!amdgpu_sriov_vf(adev)) in amdgpu_vf_error_put()
57 if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) || in amdgpu_vf_error_trans_all()
Dpsp_v13_0.c249 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_stop()
280 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_create()
362 if (amdgpu_sriov_vf(adev)) in psp_v13_0_ring_get_wptr()
374 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_set_wptr()
Dsdma_v5_0.c208 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_init_golden_registers()
251 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_NAVI12)) in sdma_v5_0_init_microcode()
658 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_ctx_switch_enable()
672 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_ctx_switch_enable()
696 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_enable()
731 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume()
783 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ in sdma_v5_0_gfx_resume()
808 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume()
814 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_gfx_resume()
837 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_gfx_resume()
[all …]
Dgmc_v9_0.c573 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_process_interrupt()
661 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_set_irq_funcs()
702 (!amdgpu_sriov_vf(adev)) && in gmc_v9_0_use_invalidate_semaphore()
766 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v9_0_flush_gpu_tlb()
1292 if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) { in gmc_v9_0_late_init()
1486 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
1537 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
1571 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_sw_init()
1654 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_init_golden_registers()
1764 if (!amdgpu_sriov_vf(adev)) { in gmc_v9_0_hw_init()
[all …]
Dmmhub_v2_0.c227 if (!amdgpu_sriov_vf(adev)) { in mmhub_v2_0_init_system_aperture_regs()
286 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_init_cache_regs()
347 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_disable_identity_aperture()
483 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_fault_enable_default()
671 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_clockgating()
698 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_get_clockgating()
Damdgpu_device.c1191 if (amdgpu_sriov_vf(adev)) in amdgpu_device_resize_fb_bar()
1266 if (amdgpu_sriov_vf(adev)) in amdgpu_device_need_post()
2076 if (amdgpu_sriov_vf(adev)) { in amdgpu_device_ip_early_init()
2174 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) in amdgpu_device_ip_early_init()
2176 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) in amdgpu_device_ip_early_init()
2218 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_early_init()
2240 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || in amdgpu_device_ip_hw_init_phase1()
2315 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) in amdgpu_device_fw_loading()
2371 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { in amdgpu_device_ip_init()
2383 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_init()
[all …]
Dpsp_v11_0.c174 if (amdgpu_sriov_vf(adev)) in psp_v11_0_init_microcode()
437 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
448 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
466 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_create()
739 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_get_wptr()
751 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_set_wptr()
Dnavi10_ih.c123 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in force_update_wptr_for_self_int()
133 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in force_update_wptr_for_self_int()
167 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in navi10_ih_toggle_ring_interrupts()
283 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in navi10_ih_enable_ring()
498 if (amdgpu_sriov_vf(adev)) in navi10_ih_set_rptr()
Damdgpu_virt.c216 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) in amdgpu_virt_alloc_mm_table()
243 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) in amdgpu_virt_free_mm_table()
702 if (amdgpu_sriov_vf(adev)) { in amdgpu_detect_virtualization()
740 if (!amdgpu_sriov_vf(adev) || in amdgpu_virt_enable_access_debugfs()
754 if (amdgpu_sriov_vf(adev)) in amdgpu_virt_disable_access_debugfs()
762 if (amdgpu_sriov_vf(adev)) { in amdgpu_virt_get_sriov_vf_mode()
Dgmc_v10_0.c129 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_process_interrupt()
160 if (!amdgpu_sriov_vf(adev)) in gmc_v10_0_process_interrupt()
182 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_set_irq_funcs()
200 (!amdgpu_sriov_vf(adev))); in gmc_v10_0_use_invalidate_semaphore()
330 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v10_0_flush_gpu_tlb()
911 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_sw_init()
1103 if (amdgpu_sriov_vf(adev)) { in gmc_v10_0_hw_fini()
Dvi.c490 if (amdgpu_sriov_vf(adev)) { in vi_init_golden_registers()
1688 if (amdgpu_sriov_vf(adev)) { in vi_common_early_init()
1700 if (amdgpu_sriov_vf(adev)) in vi_common_late_init()
1710 if (amdgpu_sriov_vf(adev)) in vi_common_sw_init()
1744 if (amdgpu_sriov_vf(adev)) in vi_common_hw_fini()
1988 if (amdgpu_sriov_vf(adev)) in vi_common_set_clockgating_state()
2037 if (amdgpu_sriov_vf(adev)) in vi_common_get_clockgating_state()
2114 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
2122 if (!amdgpu_sriov_vf(adev)) { in vi_set_ip_blocks()
2134 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
[all …]
Dvcn_v2_0.c72 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_early_init()
164 if (!amdgpu_sriov_vf(adev)) in vcn_v2_0_sw_init()
228 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_hw_init()
236 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_hw_init()
329 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_mc_resume()
487 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_disable_clock_gating()
647 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_enable_clock_gating()
701 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_disable_static_power_gating()
750 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_enable_static_power_gating()
1295 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_set_clockgating_state()
[all …]
Dgfxhub_v2_1.c214 if (amdgpu_sriov_vf(adev)) in gfxhub_v2_1_init_cache_regs()
275 if (amdgpu_sriov_vf(adev)) in gfxhub_v2_1_disable_identity_aperture()
355 if (amdgpu_sriov_vf(adev)) { in gfxhub_v2_1_gart_enable()
418 if (amdgpu_sriov_vf(adev)) in gfxhub_v2_1_set_fault_enable_default()
Dathub_v2_0.c77 if (amdgpu_sriov_vf(adev)) in athub_v2_0_set_clockgating()
Dathub_v2_1.c70 if (amdgpu_sriov_vf(adev)) in athub_v2_1_set_clockgating()
Dsdma_v5_2.c177 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID)) in sdma_v5_2_init_microcode()
662 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ in sdma_v5_2_gfx_resume()
684 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_gfx_resume()
713 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_gfx_resume()
734 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ in sdma_v5_2_gfx_resume()
852 if (amdgpu_sriov_vf(adev)) { in sdma_v5_2_start()
1350 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_hw_fini()
1621 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_set_clockgating_state()
1654 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_get_clockgating_state()

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