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Searched refs:_clk (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.15/include/linux/
Dsh_clk.h200 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } argument
201 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } argument
202 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } argument
/Linux-v5.15/arch/arm/mach-omap2/
Domap_hwmod.c635 } else if (oh->_clk) { in _get_clkdm()
636 if (!omap2_clk_is_hw_omap(__clk_get_hw(oh->_clk))) in _get_clkdm()
638 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); in _get_clkdm()
833 oh->_clk = clk; in _init_main_clk()
839 oh->_clk = clk_get(NULL, oh->main_clk); in _init_main_clk()
842 if (IS_ERR(oh->_clk)) { in _init_main_clk()
855 clk_prepare(oh->_clk); in _init_main_clk()
888 os->_clk = c; in _init_interface_clks()
897 clk_prepare(os->_clk); in _init_interface_clks()
925 oc->_clk = c; in _init_opt_clks()
[all …]
Domap_hwmod.h181 struct clk *_clk; member
244 struct clk *_clk; member
585 struct clk *_clk; member
Ddisplay.c388 clk_prepare_enable(oc->_clk); in omap_dss_reset()
414 clk_disable_unprepare(oc->_clk); in omap_dss_reset()
/Linux-v5.15/drivers/scsi/ufs/
Dufs-exynos.c342 unsigned long clk = 0, _clk, clk_period; in exynos_ufs_calc_pwm_clk_div() local
347 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div); in exynos_ufs_calc_pwm_clk_div()
348 if (_clk >= pwm_min && _clk <= pwm_max) { in exynos_ufs_calc_pwm_clk_div()
349 if (_clk > clk) { in exynos_ufs_calc_pwm_clk_div()
351 clk = _clk; in exynos_ufs_calc_pwm_clk_div()
/Linux-v5.15/Documentation/devicetree/bindings/media/
Dcdns,csi2rx.txt14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
Dcdns,csi2tx.txt15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
/Linux-v5.15/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgm20b.c852 struct gm20b_clk *_clk = gm20b_clk(base); in gm20b_clk_init() local
856 _clk->uv = nvkm_volt_get(volt); in gm20b_clk_init()
859 ret = gm20b_clk_init_dvfs(_clk); in gm20b_clk_init()
/Linux-v5.15/drivers/clk/renesas/
Dr9a06g032-clocks.c60 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \ argument
61 { .gate = _clk, .reset = _rst, \