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Searched refs:__REG (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.15/arch/arm/mach-pxa/
Dpxa27x-udc.h9 #define UDCCR __REG(0x40600000) /* UDC Control Register */
33 #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
34 #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
48 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
49 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
57 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
58 #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
85 #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
86 #define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
104 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
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Dregs-rtc.h11 #define RCNR __REG(0x40900000) /* RTC Count Register */
12 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
13 #define RTSR __REG(0x40900008) /* RTC Status Register */
14 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
15 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
Dpxa27x.h11 #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
/Linux-v5.15/arch/arm/mach-pxa/include/mach/
Dregs-uart.h11 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
12 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
13 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
14 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
15 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
16 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
17 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
18 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
19 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
20 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
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Dpxa2xx-regs.h20 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */
21 #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
22 #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
23 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
24 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
25 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
26 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
27 #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
28 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
29 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
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Dpxa3xx-regs.h26 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */
27 #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
28 #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
29 #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
30 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
31 #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
32 #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
33 #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
34 #define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
35 #define PCMD(x) __REG(0x40F50110 + ((x) << 2))
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Dregs-ac97.h11 #define POCR __REG(0x40500000) /* PCM Out Control Register */
15 #define PICR __REG(0x40500004) /* PCM In Control Register */
19 #define MCCR __REG(0x40500008) /* Mic In Control Register */
23 #define GCR __REG(0x4050000C) /* Global Control Register */
39 #define POSR __REG(0x40500010) /* PCM Out Status Register */
43 #define PISR __REG(0x40500014) /* PCM In Status Register */
48 #define MCSR __REG(0x40500018) /* Mic In Status Register */
53 #define GSR __REG(0x4050001C) /* Global Status Register */
72 #define CAR __REG(0x40500020) /* CODEC Access Register */
75 #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
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Dhardware.h40 # define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) macro
45 (*(volatile u32 __iomem*)((u32)&__REG(x) + (y)))
51 # define __REG(x) io_p2v(x) macro
/Linux-v5.15/drivers/net/ethernet/microchip/sparx5/
Dsparx5_main_regs.h54 #define __REG(...) __VA_ARGS__ macro
57 #define ANA_AC_RAM_INIT __REG(TARGET_ANA_AC, 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4)
72 #define ANA_AC_OWN_UPSID(r) __REG(TARGET_ANA_AC, 0, 1, 894472, 0, 1, 352, 52, r, 3, 4)
81 #define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 0, 0, 1, 4)
84 #define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 4, 0, 1, 4)
87 #define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 8, 0, 1, 4)
96 #define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4)
99 #define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4)
102 #define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4)
111 #define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4)
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/Linux-v5.15/arch/arm/mach-sa1100/include/mach/
DSA-1100.h111 #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
112 #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
113 #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
114 #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
115 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
116 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
117 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
118 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
119 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
120 #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */
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Dhardware.h44 # define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x))) macro
49 # define __REG(x) io_p2v(x) macro
/Linux-v5.15/drivers/phy/microchip/
Dsparx5_serdes_regs.h29 #define __REG(...) __VA_ARGS__ macro
32 #define SD10G_LANE_LANE_01(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 4, 0, 1, 4)
53 #define SD10G_LANE_LANE_02(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 8, 0, 1, 4)
86 #define SD10G_LANE_LANE_03(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 12, 0, 1, 4)
95 #define SD10G_LANE_LANE_04(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 16, 0, 1, 4)
104 #define SD10G_LANE_LANE_06(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 24, 0, 1, 4)
143 #define SD10G_LANE_LANE_0B(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 44, 0, 1, 4)
176 #define SD10G_LANE_LANE_0C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 48, 0, 1, 4)
227 #define SD10G_LANE_LANE_0D(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 52, 0, 1, 4)
242 #define SD10G_LANE_LANE_0E(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 56, 0, 1, 4)
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/Linux-v5.15/sound/soc/pxa/
Dpxa2xx-i2s.c32 #define SACR0 __REG(0x40400000) /* Global Control Register */
33 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
34 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Reg…
35 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
36 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
37 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
38 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
/Linux-v5.15/arch/xtensa/include/asm/
Dcoprocessor.h102 __REG ## list (cc, abi, type, name, size, align)