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Searched refs:_MASKED_BIT_ENABLE (Results 1 – 19 of 19) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Dreg.h98 (((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
Dmmio_context.c463 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); in is_inhibit_context()
Dhandlers.c2019 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); in ring_mode_mmio_write()
2022 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); in ring_mode_mmio_write()
2124 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); in csfe_chicken1_mmio_write()
3074 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dintel_rc6.c376 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in chv_rc6_enable()
401 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in vlv_rc6_enable()
704 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); in vlv_residency_raw()
714 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); in vlv_residency_raw()
Dintel_ggtt_fencing.c912 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in intel_gt_init_swizzling()
916 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in intel_gt_init_swizzling()
920 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); in intel_gt_init_swizzling()
Dintel_ring_submission.c116 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | in flush_cs_tlb()
160 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in set_pp_dir()
667 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); in load_pd_dir()
716 *cs++ = _MASKED_BIT_ENABLE( in mi_set_context()
1003 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); in gen6_bsd_submit_request()
Dintel_workarounds.c204 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_masked_en()
538 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), in icl_ctx_workarounds_init()
798 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), in hsw_gt_workarounds_init()
2007 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), in rcs_engine_wa_init()
2023 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), in rcs_engine_wa_init()
Dgen6_ppgtt.c66 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen6_ppgtt_enable()
Dintel_lrc.c687 ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH); in init_common_regs()
Dintel_reset.c578 intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request)); in gen8_engine_reset_prepare()
Dintel_execlists_submission.c2848 mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE); in enable_execlists()
2850 mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE); in enable_execlists()
Dintel_engine_cs.c1091 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); in __intel_engine_stop_cs()
/Linux-v5.15/drivers/gpu/drm/i915/
Dintel_pm.c401 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in _intel_set_memory_cxsr()
412 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : in _intel_set_memory_cxsr()
7656 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); in bdw_init_clock_gating()
7725 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
7729 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
7731 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
7768 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in vlv_init_clock_gating()
7806 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); in chv_init_clock_gating()
7854 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); in i965gm_init_clock_gating()
7866 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); in i965g_init_clock_gating()
[all …]
Di915_perf.c2505 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | in gen8_enable_metric_set()
2542 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | in gen12_enable_metric_set()
3948 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); in mask_reg_value()
3955 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); in mask_reg_value()
Dintel_uncore.c97 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
Di915_irq.c2827 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); in i915gm_enable_vblank()
Di915_reg.h275 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) macro
/Linux-v5.15/drivers/gpu/drm/i915/gt/uc/
Dintel_uc_fw.c473 _MASKED_BIT_ENABLE(dma_flags | START_DMA)); in uc_fw_xfer()
Dintel_guc_submission.c2328 _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); in start_engine()