Searched refs:WRITE_DATA_DST_SEL (Results 1 – 15 of 15) sorted by relevance
152 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
110 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
89 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
142 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
260 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
906 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()5205 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5213 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5221 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5229 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()6312 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6321 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()7228 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_ce_meta()7261 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_de_meta()
3286 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_wreg()4112 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4120 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4128 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4136 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
1029 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()1119 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()5502 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5511 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5535 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()5557 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
1700 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3837 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()3935 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()8727 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8736 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8869 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_ce_meta()8903 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_de_meta()
2365 WRITE_DATA_DST_SEL(0))); in gfx_v6_0_ring_emit_wreg()
1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3742 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()5684 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5698 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5705 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5716 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5727 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
5077 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5092 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5100 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
