Home
last modified time | relevance | path

Searched refs:VCS0 (Results 1 – 17 of 17) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/
Di915_pci.c350 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
360 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
369 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
400 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
451 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
524 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
535 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
602 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
612 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
665 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
[all …]
Di915_drv.h1598 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
Di915_gpu_error.c1184 case VCS0: in engine_record_registers()
Di915_irq.c4315 intel_engine_cs_irq(dev_priv->gt.engine[VCS0], in i965_irq_handler()
/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dintel_engine_types.h103 VCS0, enumerator
111 #define _VCS(n) (VCS0 + (n))
Dintel_engine_user.c163 [VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS }, in legacy_ring_idx()
Dintel_mocs.c428 [VCS0] = __GEN9_VCS0_MOCS0, in mocs_offset()
Dintel_reset.c303 [VCS0] = GEN6_GRDOM_MEDIA, in gen6_reset_engines()
498 [VCS0] = GEN11_GRDOM_MEDIA, in gen11_reset_engines()
Dintel_ring_submission.c90 case VCS0: in set_hwsp()
Dintel_engine_cs.c68 [VCS0] = {
Dintel_execlists_submission.c3363 [VCS0] = GEN8_VCS0_IRQ_SHIFT, in logical_ring_default_irqs()
/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Dmmio_context.c157 [VCS0] = 0xc900,
344 [VCS0] = 0x4264,
401 [VCS0] = 0xc900, in switch_mocs()
Dexeclist.c51 [VCS0] = VCS_AS_CONTEXT_SWITCH,
Dcmd_parser.c422 #define R_VCS1 BIT(VCS0)
604 [VCS0] = {
1158 [VCS0] = {
Dhandlers.c333 engine_mask |= BIT(VCS0); in gdrst_mmio_write()
2082 id = VCS0; in gvt_reg_tlb_control_handler()
/Linux-v5.15/drivers/gpu/drm/i915/gem/
Di915_gem_execbuffer.c2231 [I915_EXEC_BSD] = VCS0,
/Linux-v5.15/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_submission.c1266 return mask >> VCS0; in adjust_engine_mask()