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Searched refs:VCN_BASE (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dvangogh_reg_init.c42 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in vangogh_reg_base_init()
Dyellow_carp_reg_init.c42 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in yellow_carp_reg_base_init()
Dnavi10_reg_init.c41 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in navi10_reg_base_init()
Dsienna_cichlid_reg_init.c42 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in sienna_cichlid_reg_base_init()
Daldebaran_reg_init.c51 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in aldebaran_reg_base_init()
Dvega10_reg_init.c43 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in vega10_reg_base_init()
/Linux-v5.15/drivers/gpu/drm/amd/include/
Dnavi10_ip_offset.h133 static const struct IP_BASE VCN_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } }, variable
Dsienna_cichlid_ip_offset.h193 static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, variable
Dvega10_ip_offset.h83 static const struct IP_BASE __maybe_unused VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, variable
Dvangogh_ip_offset.h218 static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } }, variable
Dyellow_carp_offset.h181 static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } }, variable
Daldebaran_ip_offset.h224 static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } }, variable