1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * UFS Host Controller driver for Exynos specific extensions
4 *
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
6 * Author: Seungwon Jeon <essuuj@gmail.com>
7 * Author: Alim Akhtar <alim.akhtar@samsung.com>
8 *
9 */
10
11 #include <linux/clk.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/phy/phy.h>
16 #include <linux/platform_device.h>
17
18 #include "ufshcd.h"
19 #include "ufshcd-pltfrm.h"
20 #include "ufshci.h"
21 #include "unipro.h"
22
23 #include "ufs-exynos.h"
24
25 /*
26 * Exynos's Vendor specific registers for UFSHCI
27 */
28 #define HCI_TXPRDT_ENTRY_SIZE 0x00
29 #define PRDT_PREFECT_EN BIT(31)
30 #define PRDT_SET_SIZE(x) ((x) & 0x1F)
31 #define HCI_RXPRDT_ENTRY_SIZE 0x04
32 #define HCI_1US_TO_CNT_VAL 0x0C
33 #define CNT_VAL_1US_MASK 0x3FF
34 #define HCI_UTRL_NEXUS_TYPE 0x40
35 #define HCI_UTMRL_NEXUS_TYPE 0x44
36 #define HCI_SW_RST 0x50
37 #define UFS_LINK_SW_RST BIT(0)
38 #define UFS_UNIPRO_SW_RST BIT(1)
39 #define UFS_SW_RST_MASK (UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST)
40 #define HCI_DATA_REORDER 0x60
41 #define HCI_UNIPRO_APB_CLK_CTRL 0x68
42 #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF))
43 #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C
44 #define HCI_GPIO_OUT 0x70
45 #define HCI_ERR_EN_PA_LAYER 0x78
46 #define HCI_ERR_EN_DL_LAYER 0x7C
47 #define HCI_ERR_EN_N_LAYER 0x80
48 #define HCI_ERR_EN_T_LAYER 0x84
49 #define HCI_ERR_EN_DME_LAYER 0x88
50 #define HCI_CLKSTOP_CTRL 0xB0
51 #define REFCLK_STOP BIT(2)
52 #define UNIPRO_MCLK_STOP BIT(1)
53 #define UNIPRO_PCLK_STOP BIT(0)
54 #define CLK_STOP_MASK (REFCLK_STOP |\
55 UNIPRO_MCLK_STOP |\
56 UNIPRO_PCLK_STOP)
57 #define HCI_MISC 0xB4
58 #define REFCLK_CTRL_EN BIT(7)
59 #define UNIPRO_PCLK_CTRL_EN BIT(6)
60 #define UNIPRO_MCLK_CTRL_EN BIT(5)
61 #define HCI_CORECLK_CTRL_EN BIT(4)
62 #define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\
63 UNIPRO_PCLK_CTRL_EN |\
64 UNIPRO_MCLK_CTRL_EN)
65 /* Device fatal error */
66 #define DFES_ERR_EN BIT(31)
67 #define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\
68 UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
69 #define DFES_DEF_L3_ERRS (UIC_NETWORK_UNSUPPORTED_HEADER_TYPE |\
70 UIC_NETWORK_BAD_DEVICEID_ENC |\
71 UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING)
72 #define DFES_DEF_L4_ERRS (UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE |\
73 UIC_TRANSPORT_UNKNOWN_CPORTID |\
74 UIC_TRANSPORT_NO_CONNECTION_RX |\
75 UIC_TRANSPORT_BAD_TC)
76
77 enum {
78 UNIPRO_L1_5 = 0,/* PHY Adapter */
79 UNIPRO_L2, /* Data Link */
80 UNIPRO_L3, /* Network */
81 UNIPRO_L4, /* Transport */
82 UNIPRO_DME, /* DME */
83 };
84
85 /*
86 * UNIPRO registers
87 */
88 #define UNIPRO_COMP_VERSION 0x000
89 #define UNIPRO_DME_PWR_REQ 0x090
90 #define UNIPRO_DME_PWR_REQ_POWERMODE 0x094
91 #define UNIPRO_DME_PWR_REQ_LOCALL2TIMER0 0x098
92 #define UNIPRO_DME_PWR_REQ_LOCALL2TIMER1 0x09C
93 #define UNIPRO_DME_PWR_REQ_LOCALL2TIMER2 0x0A0
94 #define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER0 0x0A4
95 #define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER1 0x0A8
96 #define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER2 0x0AC
97
98 /*
99 * UFS Protector registers
100 */
101 #define UFSPRSECURITY 0x010
102 #define NSSMU BIT(14)
103 #define UFSPSBEGIN0 0x200
104 #define UFSPSEND0 0x204
105 #define UFSPSLUN0 0x208
106 #define UFSPSCTRL0 0x20C
107
108 #define CNTR_DIV_VAL 40
109
110 static struct exynos_ufs_drv_data exynos_ufs_drvs;
111 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en);
112 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en);
113
exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs * ufs)114 static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs)
115 {
116 exynos_ufs_auto_ctrl_hcc(ufs, true);
117 }
118
exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs * ufs)119 static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs)
120 {
121 exynos_ufs_auto_ctrl_hcc(ufs, false);
122 }
123
exynos_ufs_disable_auto_ctrl_hcc_save(struct exynos_ufs * ufs,u32 * val)124 static inline void exynos_ufs_disable_auto_ctrl_hcc_save(
125 struct exynos_ufs *ufs, u32 *val)
126 {
127 *val = hci_readl(ufs, HCI_MISC);
128 exynos_ufs_auto_ctrl_hcc(ufs, false);
129 }
130
exynos_ufs_auto_ctrl_hcc_restore(struct exynos_ufs * ufs,u32 * val)131 static inline void exynos_ufs_auto_ctrl_hcc_restore(
132 struct exynos_ufs *ufs, u32 *val)
133 {
134 hci_writel(ufs, *val, HCI_MISC);
135 }
136
exynos_ufs_gate_clks(struct exynos_ufs * ufs)137 static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs)
138 {
139 exynos_ufs_ctrl_clkstop(ufs, true);
140 }
141
exynos_ufs_ungate_clks(struct exynos_ufs * ufs)142 static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs)
143 {
144 exynos_ufs_ctrl_clkstop(ufs, false);
145 }
146
exynos7_ufs_drv_init(struct device * dev,struct exynos_ufs * ufs)147 static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
148 {
149 return 0;
150 }
151
exynos7_ufs_pre_link(struct exynos_ufs * ufs)152 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
153 {
154 struct ufs_hba *hba = ufs->hba;
155 u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
156 int i;
157
158 exynos_ufs_enable_ov_tm(hba);
159 for_each_ufs_tx_lane(ufs, i)
160 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
161 for_each_ufs_rx_lane(ufs, i) {
162 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
163 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
164 }
165 exynos_ufs_disable_ov_tm(hba);
166
167 for_each_ufs_tx_lane(ufs, i)
168 ufshcd_dme_set(hba,
169 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
170 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
171 udelay(1);
172 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
173 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
174 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
175 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
176 udelay(1600);
177 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
178
179 return 0;
180 }
181
exynos7_ufs_post_link(struct exynos_ufs * ufs)182 static int exynos7_ufs_post_link(struct exynos_ufs *ufs)
183 {
184 struct ufs_hba *hba = ufs->hba;
185 int i;
186
187 exynos_ufs_enable_ov_tm(hba);
188 for_each_ufs_tx_lane(ufs, i) {
189 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83);
190 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07);
191 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i),
192 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000)));
193 }
194 exynos_ufs_disable_ov_tm(hba);
195
196 exynos_ufs_enable_dbg_mode(hba);
197 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8);
198 exynos_ufs_disable_dbg_mode(hba);
199
200 return 0;
201 }
202
exynos7_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)203 static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs,
204 struct ufs_pa_layer_attr *pwr)
205 {
206 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE);
207
208 return 0;
209 }
210
exynos7_ufs_post_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)211 static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs,
212 struct ufs_pa_layer_attr *pwr)
213 {
214 struct ufs_hba *hba = ufs->hba;
215 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx);
216
217 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1);
218
219 if (lanes == 1) {
220 exynos_ufs_enable_dbg_mode(hba);
221 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1);
222 exynos_ufs_disable_dbg_mode(hba);
223 }
224
225 return 0;
226 }
227
228 /*
229 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
230 * Control should be disabled in the below cases
231 * - Before host controller S/W reset
232 * - Access to UFS protector's register
233 */
exynos_ufs_auto_ctrl_hcc(struct exynos_ufs * ufs,bool en)234 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en)
235 {
236 u32 misc = hci_readl(ufs, HCI_MISC);
237
238 if (en)
239 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC);
240 else
241 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC);
242 }
243
exynos_ufs_ctrl_clkstop(struct exynos_ufs * ufs,bool en)244 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en)
245 {
246 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL);
247 u32 misc = hci_readl(ufs, HCI_MISC);
248
249 if (en) {
250 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC);
251 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
252 } else {
253 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
254 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC);
255 }
256 }
257
exynos_ufs_get_clk_info(struct exynos_ufs * ufs)258 static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs)
259 {
260 struct ufs_hba *hba = ufs->hba;
261 struct list_head *head = &hba->clk_list_head;
262 struct ufs_clk_info *clki;
263 unsigned long pclk_rate;
264 u32 f_min, f_max;
265 u8 div = 0;
266 int ret = 0;
267
268 if (list_empty(head))
269 goto out;
270
271 list_for_each_entry(clki, head, list) {
272 if (!IS_ERR(clki->clk)) {
273 if (!strcmp(clki->name, "core_clk"))
274 ufs->clk_hci_core = clki->clk;
275 else if (!strcmp(clki->name, "sclk_unipro_main"))
276 ufs->clk_unipro_main = clki->clk;
277 }
278 }
279
280 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) {
281 dev_err(hba->dev, "failed to get clk info\n");
282 ret = -EINVAL;
283 goto out;
284 }
285
286 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main);
287 pclk_rate = clk_get_rate(ufs->clk_hci_core);
288 f_min = ufs->pclk_avail_min;
289 f_max = ufs->pclk_avail_max;
290
291 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
292 do {
293 pclk_rate /= (div + 1);
294
295 if (pclk_rate <= f_max)
296 break;
297 div++;
298 } while (pclk_rate >= f_min);
299 }
300
301 if (unlikely(pclk_rate < f_min || pclk_rate > f_max)) {
302 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate);
303 ret = -EINVAL;
304 goto out;
305 }
306
307 ufs->pclk_rate = pclk_rate;
308 ufs->pclk_div = div;
309
310 out:
311 return ret;
312 }
313
exynos_ufs_set_unipro_pclk_div(struct exynos_ufs * ufs)314 static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs)
315 {
316 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
317 u32 val;
318
319 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL);
320 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div),
321 HCI_UNIPRO_APB_CLK_CTRL);
322 }
323 }
324
exynos_ufs_set_pwm_clk_div(struct exynos_ufs * ufs)325 static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs)
326 {
327 struct ufs_hba *hba = ufs->hba;
328 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
329
330 ufshcd_dme_set(hba,
331 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl);
332 }
333
exynos_ufs_calc_pwm_clk_div(struct exynos_ufs * ufs)334 static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs)
335 {
336 struct ufs_hba *hba = ufs->hba;
337 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
338 const unsigned int div = 30, mult = 20;
339 const unsigned long pwm_min = 3 * 1000 * 1000;
340 const unsigned long pwm_max = 9 * 1000 * 1000;
341 const int divs[] = {32, 16, 8, 4};
342 unsigned long clk = 0, _clk, clk_period;
343 int i = 0, clk_idx = -1;
344
345 clk_period = UNIPRO_PCLK_PERIOD(ufs);
346 for (i = 0; i < ARRAY_SIZE(divs); i++) {
347 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div);
348 if (_clk >= pwm_min && _clk <= pwm_max) {
349 if (_clk > clk) {
350 clk_idx = i;
351 clk = _clk;
352 }
353 }
354 }
355
356 if (clk_idx == -1) {
357 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx);
358 dev_err(hba->dev,
359 "failed to decide pwm clock divider, will not change\n");
360 }
361
362 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK;
363 }
364
exynos_ufs_calc_time_cntr(struct exynos_ufs * ufs,long period)365 long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period)
366 {
367 const int precise = 10;
368 long pclk_rate = ufs->pclk_rate;
369 long clk_period, fraction;
370
371 clk_period = UNIPRO_PCLK_PERIOD(ufs);
372 fraction = ((NSEC_PER_SEC % pclk_rate) * precise) / pclk_rate;
373
374 return (period * precise) / ((clk_period * precise) + fraction);
375 }
376
exynos_ufs_specify_phy_time_attr(struct exynos_ufs * ufs)377 static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs)
378 {
379 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
380 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
381
382 t_cfg->tx_linereset_p =
383 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec);
384 t_cfg->tx_linereset_n =
385 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec);
386 t_cfg->tx_high_z_cnt =
387 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec);
388 t_cfg->tx_base_n_val =
389 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec);
390 t_cfg->tx_gran_n_val =
391 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec);
392 t_cfg->tx_sleep_cnt =
393 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt);
394
395 t_cfg->rx_linereset =
396 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec);
397 t_cfg->rx_hibern8_wait =
398 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec);
399 t_cfg->rx_base_n_val =
400 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec);
401 t_cfg->rx_gran_n_val =
402 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec);
403 t_cfg->rx_sleep_cnt =
404 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt);
405 t_cfg->rx_stall_cnt =
406 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt);
407 }
408
exynos_ufs_config_phy_time_attr(struct exynos_ufs * ufs)409 static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs)
410 {
411 struct ufs_hba *hba = ufs->hba;
412 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
413 int i;
414
415 exynos_ufs_set_pwm_clk_div(ufs);
416
417 exynos_ufs_enable_ov_tm(hba);
418
419 for_each_ufs_rx_lane(ufs, i) {
420 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i),
421 ufs->drv_data->uic_attr->rx_filler_enable);
422 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i),
423 RX_LINERESET(t_cfg->rx_linereset));
424 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i),
425 RX_BASE_NVAL_L(t_cfg->rx_base_n_val));
426 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i),
427 RX_BASE_NVAL_H(t_cfg->rx_base_n_val));
428 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i),
429 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val));
430 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i),
431 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val));
432 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i),
433 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt));
434 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i),
435 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt));
436 }
437
438 for_each_ufs_tx_lane(ufs, i) {
439 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i),
440 TX_LINERESET_P(t_cfg->tx_linereset_p));
441 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i),
442 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt));
443 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i),
444 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt));
445 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i),
446 TX_BASE_NVAL_L(t_cfg->tx_base_n_val));
447 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i),
448 TX_BASE_NVAL_H(t_cfg->tx_base_n_val));
449 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i),
450 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val));
451 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i),
452 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val));
453 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i),
454 TX_OV_H8_ENTER_EN |
455 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt));
456 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i),
457 ufs->drv_data->uic_attr->tx_min_activatetime);
458 }
459
460 exynos_ufs_disable_ov_tm(hba);
461 }
462
exynos_ufs_config_phy_cap_attr(struct exynos_ufs * ufs)463 static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs)
464 {
465 struct ufs_hba *hba = ufs->hba;
466 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
467 int i;
468
469 exynos_ufs_enable_ov_tm(hba);
470
471 for_each_ufs_rx_lane(ufs, i) {
472 ufshcd_dme_set(hba,
473 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i),
474 attr->rx_hs_g1_sync_len_cap);
475 ufshcd_dme_set(hba,
476 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i),
477 attr->rx_hs_g2_sync_len_cap);
478 ufshcd_dme_set(hba,
479 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i),
480 attr->rx_hs_g3_sync_len_cap);
481 ufshcd_dme_set(hba,
482 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i),
483 attr->rx_hs_g1_prep_sync_len_cap);
484 ufshcd_dme_set(hba,
485 UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i),
486 attr->rx_hs_g2_prep_sync_len_cap);
487 ufshcd_dme_set(hba,
488 UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i),
489 attr->rx_hs_g3_prep_sync_len_cap);
490 }
491
492 if (attr->rx_adv_fine_gran_sup_en == 0) {
493 for_each_ufs_rx_lane(ufs, i) {
494 ufshcd_dme_set(hba,
495 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0);
496
497 if (attr->rx_min_actv_time_cap)
498 ufshcd_dme_set(hba,
499 UIC_ARG_MIB_SEL(RX_MIN_ACTIVATETIME_CAP,
500 i), attr->rx_min_actv_time_cap);
501
502 if (attr->rx_hibern8_time_cap)
503 ufshcd_dme_set(hba,
504 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i),
505 attr->rx_hibern8_time_cap);
506 }
507 } else if (attr->rx_adv_fine_gran_sup_en == 1) {
508 for_each_ufs_rx_lane(ufs, i) {
509 if (attr->rx_adv_fine_gran_step)
510 ufshcd_dme_set(hba,
511 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP,
512 i), RX_ADV_FINE_GRAN_STEP(
513 attr->rx_adv_fine_gran_step));
514
515 if (attr->rx_adv_min_actv_time_cap)
516 ufshcd_dme_set(hba,
517 UIC_ARG_MIB_SEL(
518 RX_ADV_MIN_ACTIVATETIME_CAP, i),
519 attr->rx_adv_min_actv_time_cap);
520
521 if (attr->rx_adv_hibern8_time_cap)
522 ufshcd_dme_set(hba,
523 UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP,
524 i),
525 attr->rx_adv_hibern8_time_cap);
526 }
527 }
528
529 exynos_ufs_disable_ov_tm(hba);
530 }
531
exynos_ufs_establish_connt(struct exynos_ufs * ufs)532 static void exynos_ufs_establish_connt(struct exynos_ufs *ufs)
533 {
534 struct ufs_hba *hba = ufs->hba;
535 enum {
536 DEV_ID = 0x00,
537 PEER_DEV_ID = 0x01,
538 PEER_CPORT_ID = 0x00,
539 TRAFFIC_CLASS = 0x00,
540 };
541
542 /* allow cport attributes to be set */
543 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE);
544
545 /* local unipro attributes */
546 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID);
547 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), TRUE);
548 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID);
549 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID);
550 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS);
551 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS);
552 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED);
553 }
554
exynos_ufs_config_smu(struct exynos_ufs * ufs)555 static void exynos_ufs_config_smu(struct exynos_ufs *ufs)
556 {
557 u32 reg, val;
558
559 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
560
561 /* make encryption disabled by default */
562 reg = ufsp_readl(ufs, UFSPRSECURITY);
563 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY);
564 ufsp_writel(ufs, 0x0, UFSPSBEGIN0);
565 ufsp_writel(ufs, 0xffffffff, UFSPSEND0);
566 ufsp_writel(ufs, 0xff, UFSPSLUN0);
567 ufsp_writel(ufs, 0xf1, UFSPSCTRL0);
568
569 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
570 }
571
exynos_ufs_config_sync_pattern_mask(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)572 static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs,
573 struct ufs_pa_layer_attr *pwr)
574 {
575 struct ufs_hba *hba = ufs->hba;
576 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx);
577 u32 mask, sync_len;
578 enum {
579 SYNC_LEN_G1 = 80 * 1000, /* 80us */
580 SYNC_LEN_G2 = 40 * 1000, /* 44us */
581 SYNC_LEN_G3 = 20 * 1000, /* 20us */
582 };
583 int i;
584
585 if (g == 1)
586 sync_len = SYNC_LEN_G1;
587 else if (g == 2)
588 sync_len = SYNC_LEN_G2;
589 else if (g == 3)
590 sync_len = SYNC_LEN_G3;
591 else
592 return;
593
594 mask = exynos_ufs_calc_time_cntr(ufs, sync_len);
595 mask = (mask >> 8) & 0xff;
596
597 exynos_ufs_enable_ov_tm(hba);
598
599 for_each_ufs_rx_lane(ufs, i)
600 ufshcd_dme_set(hba,
601 UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask);
602
603 exynos_ufs_disable_ov_tm(hba);
604 }
605
exynos_ufs_pre_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)606 static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
607 struct ufs_pa_layer_attr *dev_max_params,
608 struct ufs_pa_layer_attr *dev_req_params)
609 {
610 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
611 struct phy *generic_phy = ufs->phy;
612 struct ufs_dev_params ufs_exynos_cap;
613 int ret;
614
615 if (!dev_req_params) {
616 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
617 ret = -EINVAL;
618 goto out;
619 }
620
621 ufshcd_init_pwr_dev_param(&ufs_exynos_cap);
622
623 ret = ufshcd_get_pwr_dev_param(&ufs_exynos_cap,
624 dev_max_params, dev_req_params);
625 if (ret) {
626 pr_err("%s: failed to determine capabilities\n", __func__);
627 goto out;
628 }
629
630 if (ufs->drv_data->pre_pwr_change)
631 ufs->drv_data->pre_pwr_change(ufs, dev_req_params);
632
633 if (ufshcd_is_hs_mode(dev_req_params)) {
634 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params);
635
636 switch (dev_req_params->hs_rate) {
637 case PA_HS_MODE_A:
638 case PA_HS_MODE_B:
639 phy_calibrate(generic_phy);
640 break;
641 }
642 }
643
644 /* setting for three timeout values for traffic class #0 */
645 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);
646 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224);
647 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);
648
649 return 0;
650 out:
651 return ret;
652 }
653
654 #define PWR_MODE_STR_LEN 64
exynos_ufs_post_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * pwr_req)655 static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba,
656 struct ufs_pa_layer_attr *pwr_req)
657 {
658 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
659 struct phy *generic_phy = ufs->phy;
660 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx);
661 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx);
662 char pwr_str[PWR_MODE_STR_LEN] = "";
663
664 /* let default be PWM Gear 1, Lane 1 */
665 if (!gear)
666 gear = 1;
667
668 if (!lanes)
669 lanes = 1;
670
671 if (ufs->drv_data->post_pwr_change)
672 ufs->drv_data->post_pwr_change(ufs, pwr_req);
673
674 if ((ufshcd_is_hs_mode(pwr_req))) {
675 switch (pwr_req->hs_rate) {
676 case PA_HS_MODE_A:
677 case PA_HS_MODE_B:
678 phy_calibrate(generic_phy);
679 break;
680 }
681
682 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s series_%s G_%d L_%d",
683 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B",
684 gear, lanes);
685 } else {
686 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s G_%d L_%d",
687 "SLOW", gear, lanes);
688 }
689
690 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str);
691
692 return 0;
693 }
694
exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba * hba,int tag,bool op)695 static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba,
696 int tag, bool op)
697 {
698 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
699 u32 type;
700
701 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
702
703 if (op)
704 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE);
705 else
706 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE);
707 }
708
exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba * hba,int tag,u8 func)709 static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba,
710 int tag, u8 func)
711 {
712 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
713 u32 type;
714
715 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE);
716
717 switch (func) {
718 case UFS_ABORT_TASK:
719 case UFS_QUERY_TASK:
720 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE);
721 break;
722 case UFS_ABORT_TASK_SET:
723 case UFS_CLEAR_TASK_SET:
724 case UFS_LOGICAL_RESET:
725 case UFS_QUERY_TASK_SET:
726 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE);
727 break;
728 }
729 }
730
exynos_ufs_phy_init(struct exynos_ufs * ufs)731 static int exynos_ufs_phy_init(struct exynos_ufs *ufs)
732 {
733 struct ufs_hba *hba = ufs->hba;
734 struct phy *generic_phy = ufs->phy;
735 int ret = 0;
736
737 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) {
738 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),
739 &ufs->avail_ln_rx);
740 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),
741 &ufs->avail_ln_tx);
742 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx,
743 "available data lane is not equal(rx:%d, tx:%d)\n",
744 ufs->avail_ln_rx, ufs->avail_ln_tx);
745 }
746
747 phy_set_bus_width(generic_phy, ufs->avail_ln_rx);
748 ret = phy_init(generic_phy);
749 if (ret) {
750 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
751 __func__, ret);
752 goto out_exit_phy;
753 }
754
755 return 0;
756
757 out_exit_phy:
758 phy_exit(generic_phy);
759
760 return ret;
761 }
762
exynos_ufs_config_unipro(struct exynos_ufs * ufs)763 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
764 {
765 struct ufs_hba *hba = ufs->hba;
766
767 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
768 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
769 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS),
770 ufs->drv_data->uic_attr->tx_trailingclks);
771 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE),
772 ufs->drv_data->uic_attr->pa_dbg_option_suite);
773 }
774
exynos_ufs_config_intr(struct exynos_ufs * ufs,u32 errs,u8 index)775 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
776 {
777 switch (index) {
778 case UNIPRO_L1_5:
779 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER);
780 break;
781 case UNIPRO_L2:
782 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER);
783 break;
784 case UNIPRO_L3:
785 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER);
786 break;
787 case UNIPRO_L4:
788 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER);
789 break;
790 case UNIPRO_DME:
791 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER);
792 break;
793 }
794 }
795
exynos_ufs_pre_link(struct ufs_hba * hba)796 static int exynos_ufs_pre_link(struct ufs_hba *hba)
797 {
798 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
799
800 /* hci */
801 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2);
802 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3);
803 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4);
804 exynos_ufs_set_unipro_pclk_div(ufs);
805
806 /* unipro */
807 exynos_ufs_config_unipro(ufs);
808
809 /* m-phy */
810 exynos_ufs_phy_init(ufs);
811 exynos_ufs_config_phy_time_attr(ufs);
812 exynos_ufs_config_phy_cap_attr(ufs);
813
814 if (ufs->drv_data->pre_link)
815 ufs->drv_data->pre_link(ufs);
816
817 return 0;
818 }
819
exynos_ufs_fit_aggr_timeout(struct exynos_ufs * ufs)820 static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs)
821 {
822 u32 val;
823
824 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL);
825 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL);
826 }
827
exynos_ufs_post_link(struct ufs_hba * hba)828 static int exynos_ufs_post_link(struct ufs_hba *hba)
829 {
830 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
831 struct phy *generic_phy = ufs->phy;
832 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
833
834 exynos_ufs_establish_connt(ufs);
835 exynos_ufs_fit_aggr_timeout(ufs);
836
837 hci_writel(ufs, 0xa, HCI_DATA_REORDER);
838 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_TXPRDT_ENTRY_SIZE);
839 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_RXPRDT_ENTRY_SIZE);
840 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE);
841 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE);
842 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN);
843
844 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)
845 ufshcd_dme_set(hba,
846 UIC_ARG_MIB(T_DBG_SKIP_INIT_HIBERN8_EXIT), TRUE);
847
848 if (attr->pa_granularity) {
849 exynos_ufs_enable_dbg_mode(hba);
850 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY),
851 attr->pa_granularity);
852 exynos_ufs_disable_dbg_mode(hba);
853
854 if (attr->pa_tactivate)
855 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
856 attr->pa_tactivate);
857 if (attr->pa_hibern8time &&
858 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER))
859 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
860 attr->pa_hibern8time);
861 }
862
863 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
864 if (!attr->pa_granularity)
865 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
866 &attr->pa_granularity);
867 if (!attr->pa_hibern8time)
868 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
869 &attr->pa_hibern8time);
870 /*
871 * not wait for HIBERN8 time to exit hibernation
872 */
873 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0);
874
875 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) {
876 /* Valid range for granularity: 1 ~ 6 */
877 dev_warn(hba->dev,
878 "%s: pa_granularity %d is invalid, assuming backwards compatibility\n",
879 __func__,
880 attr->pa_granularity);
881 attr->pa_granularity = 6;
882 }
883 }
884
885 phy_calibrate(generic_phy);
886
887 if (ufs->drv_data->post_link)
888 ufs->drv_data->post_link(ufs);
889
890 return 0;
891 }
892
exynos_ufs_parse_dt(struct device * dev,struct exynos_ufs * ufs)893 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
894 {
895 struct device_node *np = dev->of_node;
896 struct exynos_ufs_drv_data *drv_data = &exynos_ufs_drvs;
897 struct exynos_ufs_uic_attr *attr;
898 int ret = 0;
899
900 while (drv_data->compatible) {
901 if (of_device_is_compatible(np, drv_data->compatible)) {
902 ufs->drv_data = drv_data;
903 break;
904 }
905 drv_data++;
906 }
907
908 if (ufs->drv_data && ufs->drv_data->uic_attr) {
909 attr = ufs->drv_data->uic_attr;
910 } else {
911 dev_err(dev, "failed to get uic attributes\n");
912 ret = -EINVAL;
913 goto out;
914 }
915
916 ufs->pclk_avail_min = PCLK_AVAIL_MIN;
917 ufs->pclk_avail_max = PCLK_AVAIL_MAX;
918
919 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN;
920 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL;
921 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP;
922 attr->pa_granularity = PA_GRANULARITY_VAL;
923 attr->pa_tactivate = PA_TACTIVATE_VAL;
924 attr->pa_hibern8time = PA_HIBERN8TIME_VAL;
925
926 out:
927 return ret;
928 }
929
exynos_ufs_init(struct ufs_hba * hba)930 static int exynos_ufs_init(struct ufs_hba *hba)
931 {
932 struct device *dev = hba->dev;
933 struct platform_device *pdev = to_platform_device(dev);
934 struct exynos_ufs *ufs;
935 int ret;
936
937 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
938 if (!ufs)
939 return -ENOMEM;
940
941 /* exynos-specific hci */
942 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
943 if (IS_ERR(ufs->reg_hci)) {
944 dev_err(dev, "cannot ioremap for hci vendor register\n");
945 return PTR_ERR(ufs->reg_hci);
946 }
947
948 /* unipro */
949 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro");
950 if (IS_ERR(ufs->reg_unipro)) {
951 dev_err(dev, "cannot ioremap for unipro register\n");
952 return PTR_ERR(ufs->reg_unipro);
953 }
954
955 /* ufs protector */
956 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp");
957 if (IS_ERR(ufs->reg_ufsp)) {
958 dev_err(dev, "cannot ioremap for ufs protector register\n");
959 return PTR_ERR(ufs->reg_ufsp);
960 }
961
962 ret = exynos_ufs_parse_dt(dev, ufs);
963 if (ret) {
964 dev_err(dev, "failed to get dt info.\n");
965 goto out;
966 }
967
968 ufs->phy = devm_phy_get(dev, "ufs-phy");
969 if (IS_ERR(ufs->phy)) {
970 ret = PTR_ERR(ufs->phy);
971 dev_err(dev, "failed to get ufs-phy\n");
972 goto out;
973 }
974
975 ret = phy_power_on(ufs->phy);
976 if (ret)
977 goto phy_off;
978
979 ufs->hba = hba;
980 ufs->opts = ufs->drv_data->opts;
981 ufs->rx_sel_idx = PA_MAXDATALANES;
982 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX)
983 ufs->rx_sel_idx = 0;
984 hba->priv = (void *)ufs;
985 hba->quirks = ufs->drv_data->quirks;
986 if (ufs->drv_data->drv_init) {
987 ret = ufs->drv_data->drv_init(dev, ufs);
988 if (ret) {
989 dev_err(dev, "failed to init drv-data\n");
990 goto out;
991 }
992 }
993
994 ret = exynos_ufs_get_clk_info(ufs);
995 if (ret)
996 goto out;
997 exynos_ufs_specify_phy_time_attr(ufs);
998 exynos_ufs_config_smu(ufs);
999 return 0;
1000
1001 phy_off:
1002 phy_power_off(ufs->phy);
1003 out:
1004 hba->priv = NULL;
1005 return ret;
1006 }
1007
exynos_ufs_host_reset(struct ufs_hba * hba)1008 static int exynos_ufs_host_reset(struct ufs_hba *hba)
1009 {
1010 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1011 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1012 u32 val;
1013 int ret = 0;
1014
1015 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
1016
1017 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST);
1018
1019 do {
1020 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK))
1021 goto out;
1022 } while (time_before(jiffies, timeout));
1023
1024 dev_err(hba->dev, "timeout host sw-reset\n");
1025 ret = -ETIMEDOUT;
1026
1027 out:
1028 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
1029 return ret;
1030 }
1031
exynos_ufs_dev_hw_reset(struct ufs_hba * hba)1032 static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba)
1033 {
1034 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1035
1036 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT);
1037 udelay(5);
1038 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT);
1039 }
1040
exynos_ufs_pre_hibern8(struct ufs_hba * hba,u8 enter)1041 static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, u8 enter)
1042 {
1043 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1044 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1045
1046 if (!enter) {
1047 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1048 exynos_ufs_disable_auto_ctrl_hcc(ufs);
1049 exynos_ufs_ungate_clks(ufs);
1050
1051 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1052 static const unsigned int granularity_tbl[] = {
1053 1, 4, 8, 16, 32, 100
1054 };
1055 int h8_time = attr->pa_hibern8time *
1056 granularity_tbl[attr->pa_granularity - 1];
1057 unsigned long us;
1058 s64 delta;
1059
1060 do {
1061 delta = h8_time - ktime_us_delta(ktime_get(),
1062 ufs->entry_hibern8_t);
1063 if (delta <= 0)
1064 break;
1065
1066 us = min_t(s64, delta, USEC_PER_MSEC);
1067 if (us >= 10)
1068 usleep_range(us, us + 10);
1069 } while (1);
1070 }
1071 }
1072 }
1073
exynos_ufs_post_hibern8(struct ufs_hba * hba,u8 enter)1074 static void exynos_ufs_post_hibern8(struct ufs_hba *hba, u8 enter)
1075 {
1076 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1077
1078 if (!enter) {
1079 u32 cur_mode = 0;
1080 u32 pwrmode;
1081
1082 if (ufshcd_is_hs_mode(&ufs->dev_req_params))
1083 pwrmode = FAST_MODE;
1084 else
1085 pwrmode = SLOW_MODE;
1086
1087 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode);
1088 if (cur_mode != (pwrmode << 4 | pwrmode)) {
1089 dev_warn(hba->dev, "%s: power mode change\n", __func__);
1090 hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf;
1091 hba->pwr_info.pwr_tx = cur_mode & 0xf;
1092 ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
1093 }
1094
1095 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB))
1096 exynos_ufs_establish_connt(ufs);
1097 } else {
1098 ufs->entry_hibern8_t = ktime_get();
1099 exynos_ufs_gate_clks(ufs);
1100 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1101 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1102 }
1103 }
1104
exynos_ufs_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1105 static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba,
1106 enum ufs_notify_change_status status)
1107 {
1108 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1109 int ret = 0;
1110
1111 switch (status) {
1112 case PRE_CHANGE:
1113 ret = exynos_ufs_host_reset(hba);
1114 if (ret)
1115 return ret;
1116 exynos_ufs_dev_hw_reset(hba);
1117 break;
1118 case POST_CHANGE:
1119 exynos_ufs_calc_pwm_clk_div(ufs);
1120 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL))
1121 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1122 break;
1123 }
1124
1125 return ret;
1126 }
1127
exynos_ufs_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1128 static int exynos_ufs_link_startup_notify(struct ufs_hba *hba,
1129 enum ufs_notify_change_status status)
1130 {
1131 int ret = 0;
1132
1133 switch (status) {
1134 case PRE_CHANGE:
1135 ret = exynos_ufs_pre_link(hba);
1136 break;
1137 case POST_CHANGE:
1138 ret = exynos_ufs_post_link(hba);
1139 break;
1140 }
1141
1142 return ret;
1143 }
1144
exynos_ufs_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)1145 static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba,
1146 enum ufs_notify_change_status status,
1147 struct ufs_pa_layer_attr *dev_max_params,
1148 struct ufs_pa_layer_attr *dev_req_params)
1149 {
1150 int ret = 0;
1151
1152 switch (status) {
1153 case PRE_CHANGE:
1154 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params,
1155 dev_req_params);
1156 break;
1157 case POST_CHANGE:
1158 ret = exynos_ufs_post_pwr_mode(hba, dev_req_params);
1159 break;
1160 }
1161
1162 return ret;
1163 }
1164
exynos_ufs_hibern8_notify(struct ufs_hba * hba,enum uic_cmd_dme enter,enum ufs_notify_change_status notify)1165 static void exynos_ufs_hibern8_notify(struct ufs_hba *hba,
1166 enum uic_cmd_dme enter,
1167 enum ufs_notify_change_status notify)
1168 {
1169 switch ((u8)notify) {
1170 case PRE_CHANGE:
1171 exynos_ufs_pre_hibern8(hba, enter);
1172 break;
1173 case POST_CHANGE:
1174 exynos_ufs_post_hibern8(hba, enter);
1175 break;
1176 }
1177 }
1178
exynos_ufs_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op)1179 static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
1180 {
1181 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1182
1183 if (!ufshcd_is_link_active(hba))
1184 phy_power_off(ufs->phy);
1185
1186 return 0;
1187 }
1188
exynos_ufs_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)1189 static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
1190 {
1191 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1192
1193 if (!ufshcd_is_link_active(hba))
1194 phy_power_on(ufs->phy);
1195
1196 exynos_ufs_config_smu(ufs);
1197
1198 return 0;
1199 }
1200
1201 static struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
1202 .name = "exynos_ufs",
1203 .init = exynos_ufs_init,
1204 .hce_enable_notify = exynos_ufs_hce_enable_notify,
1205 .link_startup_notify = exynos_ufs_link_startup_notify,
1206 .pwr_change_notify = exynos_ufs_pwr_change_notify,
1207 .setup_xfer_req = exynos_ufs_specify_nexus_t_xfer_req,
1208 .setup_task_mgmt = exynos_ufs_specify_nexus_t_tm_req,
1209 .hibern8_notify = exynos_ufs_hibern8_notify,
1210 .suspend = exynos_ufs_suspend,
1211 .resume = exynos_ufs_resume,
1212 };
1213
exynos_ufs_probe(struct platform_device * pdev)1214 static int exynos_ufs_probe(struct platform_device *pdev)
1215 {
1216 int err;
1217 struct device *dev = &pdev->dev;
1218
1219 err = ufshcd_pltfrm_init(pdev, &ufs_hba_exynos_ops);
1220 if (err)
1221 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1222
1223 return err;
1224 }
1225
exynos_ufs_remove(struct platform_device * pdev)1226 static int exynos_ufs_remove(struct platform_device *pdev)
1227 {
1228 struct ufs_hba *hba = platform_get_drvdata(pdev);
1229
1230 pm_runtime_get_sync(&(pdev)->dev);
1231 ufshcd_remove(hba);
1232 return 0;
1233 }
1234
1235 static struct exynos_ufs_uic_attr exynos7_uic_attr = {
1236 .tx_trailingclks = 0x10,
1237 .tx_dif_p_nsec = 3000000, /* unit: ns */
1238 .tx_dif_n_nsec = 1000000, /* unit: ns */
1239 .tx_high_z_cnt_nsec = 20000, /* unit: ns */
1240 .tx_base_unit_nsec = 100000, /* unit: ns */
1241 .tx_gran_unit_nsec = 4000, /* unit: ns */
1242 .tx_sleep_cnt = 1000, /* unit: ns */
1243 .tx_min_activatetime = 0xa,
1244 .rx_filler_enable = 0x2,
1245 .rx_dif_p_nsec = 1000000, /* unit: ns */
1246 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
1247 .rx_base_unit_nsec = 100000, /* unit: ns */
1248 .rx_gran_unit_nsec = 4000, /* unit: ns */
1249 .rx_sleep_cnt = 1280, /* unit: ns */
1250 .rx_stall_cnt = 320, /* unit: ns */
1251 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
1252 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
1253 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
1254 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
1255 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
1256 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
1257 .pa_dbg_option_suite = 0x30103,
1258 };
1259
1260 static struct exynos_ufs_drv_data exynos_ufs_drvs = {
1261 .compatible = "samsung,exynos7-ufs",
1262 .uic_attr = &exynos7_uic_attr,
1263 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1264 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
1265 UFSHCI_QUIRK_BROKEN_HCE |
1266 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
1267 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1268 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL |
1269 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING |
1270 UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE,
1271 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
1272 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
1273 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX |
1274 EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB |
1275 EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER,
1276 .drv_init = exynos7_ufs_drv_init,
1277 .pre_link = exynos7_ufs_pre_link,
1278 .post_link = exynos7_ufs_post_link,
1279 .pre_pwr_change = exynos7_ufs_pre_pwr_change,
1280 .post_pwr_change = exynos7_ufs_post_pwr_change,
1281 };
1282
1283 static const struct of_device_id exynos_ufs_of_match[] = {
1284 { .compatible = "samsung,exynos7-ufs",
1285 .data = &exynos_ufs_drvs },
1286 {},
1287 };
1288
1289 static const struct dev_pm_ops exynos_ufs_pm_ops = {
1290 SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
1291 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1292 .prepare = ufshcd_suspend_prepare,
1293 .complete = ufshcd_resume_complete,
1294 };
1295
1296 static struct platform_driver exynos_ufs_pltform = {
1297 .probe = exynos_ufs_probe,
1298 .remove = exynos_ufs_remove,
1299 .shutdown = ufshcd_pltfrm_shutdown,
1300 .driver = {
1301 .name = "exynos-ufshc",
1302 .pm = &exynos_ufs_pm_ops,
1303 .of_match_table = of_match_ptr(exynos_ufs_of_match),
1304 },
1305 };
1306 module_platform_driver(exynos_ufs_pltform);
1307
1308 MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>");
1309 MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>");
1310 MODULE_DESCRIPTION("Exynos UFS HCI Driver");
1311 MODULE_LICENSE("GPL v2");
1312
