Searched refs:UMC (Results 1 – 7 of 7) sorted by relevance
103 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()106 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()111 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()114 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()181 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT); in umc_v6_1_query_correctable_error_count()183 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT); in umc_v6_1_query_correctable_error_count()185 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT); in umc_v6_1_query_correctable_error_count()189 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); in umc_v6_1_query_correctable_error_count()191 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); in umc_v6_1_query_correctable_error_count()193 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_1_query_correctable_error_count()[all …]
57 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_clear_error_count_per_channel()59 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_clear_error_count_per_channel()115 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_query_correctable_error_count()117 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_query_correctable_error_count()119 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_query_correctable_error_count()158 mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_querry_uncorrectable_error_count()208 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_query_error_address()210 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v8_7_query_error_address()290 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_err_cnt_init_per_channel()292 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_err_cnt_init_per_channel()
64 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCntSel); in umc_v6_7_query_correctable_error_count()66 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCnt); in umc_v6_7_query_correctable_error_count()68 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_7_query_correctable_error_count()107 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_7_querry_uncorrectable_error_count()127 SOC15_REG_OFFSET(UMC, 0, in umc_v6_7_reset_error_count_per_channel()130 SOC15_REG_OFFSET(UMC, 0, in umc_v6_7_reset_error_count_per_channel()214 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_7_query_error_address()216 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v6_7_query_error_address()
9 Controller (UMC).
15 UMC 486SX-S and the NexGen Nx586.23 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.58 AMD/Cyrix/IBM/Intel SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5S.65 486DX/DX2/DX4 and UMC U5D.487 bool "Support UMC processors" if PROCESSOR_SELECT490 This enables detection, tunings and quirks for UMC processors493 UMC CPU. Disabling this option on other types of CPUs494 makes the kernel a tiny bit smaller. Disabling it on a UMC
2221 UMC = 0x02, enumerator
4323 return UMC; in be_convert_mc_type()5767 case UMC: in mc_name()
