Searched refs:TRCEVENTCTL0R (Results 1 – 3 of 3) sorted by relevance
53 if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) || in etm4_cfg_map_reg_offset()57 CHECKREG(TRCEVENTCTL0R, eventctrl0); in etm4_cfg_map_reg_offset()
30 #define TRCEVENTCTL0R 0x020 macro186 CASE_##op((val), TRCEVENTCTL0R) \
371 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R); in etm4_enable_hw()1598 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R); in etm4_cpu_save()1711 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R); in etm4_cpu_restore()
