Searched refs:TRCCIDCCTLR0 (Results 1 – 3 of 3) sorted by relevance
55 ((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) { in etm4_cfg_map_reg_offset()71 CHECKREG(TRCCIDCCTLR0, ctxid_mask0); in etm4_cfg_map_reg_offset()
98 #define TRCCIDCCTLR0 0x680 macro358 CASE_##op((val), TRCCIDCCTLR0) \
418 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0); in etm4_enable_hw()1659 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0); in etm4_cpu_save()1765 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0); in etm4_cpu_restore()
