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Searched refs:TIME_STAMP_INT_ENABLE (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/radeon/
Dcik.c7051 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7052 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7053 cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7054 cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7055 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7056 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7057 cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7058 cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7071 cp_m1p0 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
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Dcikd.h1337 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
1369 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Dnid.h497 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Devergreen.c4526 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4530 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4534 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4540 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
Dsid.h1282 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Devergreend.h1250 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Dsi.c6078 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6082 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6086 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
Dr600d.h718 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Dr600.c3822 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dsid.h1310 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Dgfx_v9_0.c5713 TIME_STAMP_INT_ENABLE, in gfx_v9_0_set_gfx_eop_interrupt_state()
5760 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_0_set_compute_eop_interrupt_state()
5766 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_0_set_compute_eop_interrupt_state()
Dgfx_v10_0.c9035 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_gfx_eop_interrupt_state()
9041 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_gfx_eop_interrupt_state()
9088 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_compute_eop_interrupt_state()
9094 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_compute_eop_interrupt_state()
Dgfx_v8_0.c6450 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_gfx_eop_interrupt_state()