Searched refs:TEGRA186_CLK_PLL_A_OUT0 (Results 1 – 2 of 2) sorted by relevance
150 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;210 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;224 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;238 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;292 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;304 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;316 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;[all …]
712 #define TEGRA186_CLK_PLL_A_OUT0 246 macro
