Searched refs:SPRN_L1CSR1 (Results 1 – 5 of 5) sorted by relevance
226 tmp = mfspr(SPRN_L1CSR1); in flush_instruction_cache()228 mtspr(SPRN_L1CSR1, tmp); in flush_instruction_cache()
20 mfspr r0, SPRN_L1CSR125 mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
627 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); in machine_check_e500mc()628 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) in machine_check_e500mc()
252 case SPRN_L1CSR1: in kvmppc_core_emulate_mtspr_e500()381 case SPRN_L1CSR1: in kvmppc_core_emulate_mfspr_e500()
174 #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ macro
