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Searched refs:SOC15_WAIT_ON_RREG (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c703 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF); in vcn_1_0_disable_static_power_gating()
717 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF); in vcn_1_0_disable_static_power_gating()
767 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF); in vcn_1_0_enable_static_power_gating()
1118 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode()
1124 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v1_0_stop_spg_mode()
1133 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v1_0_stop_spg_mode()
1165 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1171 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1174 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1177 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
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Dvcn_v2_0.c717 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, in vcn_v2_0_disable_static_power_gating()
731 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF); in vcn_v2_0_disable_static_power_gating()
784 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF); in vcn_v2_0_enable_static_power_gating()
1103 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
1108 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1111 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1114 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1116 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
1139 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop()
1147 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_0_stop()
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Dvcn_v3_0.c629 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, in vcn_v3_0_disable_static_power_gating()
647 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); in vcn_v3_0_disable_static_power_gating()
700 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); in vcn_v3_0_enable_static_power_gating()
750 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v3_0_disable_clock_gating()
1514 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1519 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1522 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1525 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1527 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1552 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v3_0_stop()
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Dvcn_v2_5.c588 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v2_5_disable_clock_gating()
1304 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1309 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1312 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1315 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1317 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1341 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop()
1349 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1360 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1410 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v2_5_pause_dpg_mode()
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Djpeg_v3_0.c269 r = SOC15_WAIT_ON_RREG(JPEG, 0, in jpeg_v3_0_disable_static_power_gating()
304 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, in jpeg_v3_0_enable_static_power_gating()
465 return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, in jpeg_v3_0_wait_for_idle()
Djpeg_v2_0.c235 r = SOC15_WAIT_ON_RREG(JPEG, 0, in jpeg_v2_0_disable_power_gating()
266 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, in jpeg_v2_0_enable_power_gating()
688 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, in jpeg_v2_0_wait_for_idle()
Dsoc15_common.h76 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \ macro
Djpeg_v2_5.c452 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, in jpeg_v2_5_wait_for_idle()