Searched refs:SOC15_REG_ENTRY_OFFSET (Results 1 – 7 of 7) sorted by relevance
382 ib->ptr[ib->length_dw++] = SOC15_REG_ENTRY_OFFSET(init_regs[i]) in gfx_v9_4_2_run_shader()1504 WREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_2_query_sram_edc_count()1509 data = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_2_query_sram_edc_count()1520 WREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_2_query_sram_edc_count()1607 WREG32(SOC15_REG_ENTRY_OFFSET(blk->idx_reg), j); in gfx_v9_4_2_query_utc_edc_count()1611 WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg), in gfx_v9_4_2_query_utc_edc_count()1616 data = RREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg)); in gfx_v9_4_2_query_utc_edc_count()1626 WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg), in gfx_v9_4_2_query_utc_edc_count()1679 value = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_2_reset_ea_err_status()1682 WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), value); in gfx_v9_4_2_reset_ea_err_status()[all …]
91 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.… macro
1257 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i])); in mmhub_v1_7_query_ras_error_count()1274 WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]), 0); in mmhub_v1_7_reset_ras_error_count()1297 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i])); in mmhub_v1_7_query_ras_error_status()1316 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( in mmhub_v1_7_reset_ras_error_status()1320 WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]), in mmhub_v1_7_reset_ras_error_status()
887 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_query_ras_error_count()922 RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_reset_ras_error_count()1014 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_query_ras_error_status()
756 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); in mmhub_v1_0_query_ras_error_count()774 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); in mmhub_v1_0_reset_ras_error_count()
1605 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i])); in mmhub_v9_4_query_ras_error_count()1622 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i])); in mmhub_v9_4_reset_ras_error_count()1647 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_err_status_regs[i])); in mmhub_v9_4_query_ras_error_status()
4630 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) in gfx_v9_0_do_edc_gpr_workarounds()4658 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) in gfx_v9_0_do_edc_gpr_workarounds()4686 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) in gfx_v9_0_do_edc_gpr_workarounds()6678 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); in gfx_v9_0_reset_ras_error_count()6741 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); in gfx_v9_0_query_ras_error_count()
