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Searched refs:SDMA1_REGISTER_OFFSET (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/radeon/
Dcik_sdma.c73 reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_get_rptr()
97 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_get_wptr()
118 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_set_wptr()
262 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_stop()
312 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
344 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_enable()
379 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_resume()
492 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_sdma_load_microcode()
494 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++)); in cik_sdma_load_microcode()
495 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); in cik_sdma_load_microcode()
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Dcik.c166 case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET): in cik_get_allowed_info_register()
3328 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
4814 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
4871 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
4960 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset()
4962 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5161 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5163 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5514 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5515 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
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Dcikd.h1953 #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dcik_sdma.c50 SDMA1_REGISTER_OFFSET
895 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
902 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
905 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
920 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
923 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
930 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
933 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
1089 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_soft_reset()
1091 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
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Dsdma_v2_4.c63 SDMA1_REGISTER_OFFSET
983 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
985 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
1036 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1038 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1041 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1043 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
Dsdma_v3_0.c77 SDMA1_REGISTER_OFFSET
1370 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1372 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1375 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1377 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
Damdgpu_amdkfd_gfx_v8.c149 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + in get_sdma_rlc_reg_offset()
339 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + in kgd_hqd_sdma_dump()
Damdgpu_amdkfd_gfx_v7.c191 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + in get_sdma_rlc_reg_offset()
353 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + in kgd_hqd_sdma_dump()
Dvid.h27 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ macro
Dcikd.h485 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ macro
Dcik.c1053 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
Dvi.c675 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},