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Searched refs:SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_sh_mask.h544 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT … macro
Dsdma0_4_0_sh_mask.h545 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 macro
Dsdma0_4_2_2_sh_mask.h551 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT … macro
Dsdma0_4_2_sh_mask.h545 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT … macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_0_sh_mask.h966 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 macro
Doss_2_4_sh_mask.h1050 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 macro
Doss_3_0_1_sh_mask.h1068 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 macro
Doss_3_0_sh_mask.h1574 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/sdma/
Dsdma_4_4_0_sh_mask.h236 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT … macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_3_0_sh_mask.h254 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT … macro
Dgc_10_1_0_sh_mask.h253 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT … macro