Searched refs:RREG8 (Results 1 – 12 of 12) sorted by relevance
370 tmp = RREG8(MGAREG_CRTC_DATA); in mgag200_pixpll_update_g200wb()377 tmp = RREG8(DAC_DATA); in mgag200_pixpll_update_g200wb()382 tmp = RREG8(DAC_DATA); in mgag200_pixpll_update_g200wb()387 tmp = RREG8(MGAREG_MEM_MISC_READ); in mgag200_pixpll_update_g200wb()392 tmp = RREG8(DAC_DATA); in mgag200_pixpll_update_g200wb()400 tmp = RREG8(DAC_DATA); in mgag200_pixpll_update_g200wb()415 tmp = RREG8(DAC_DATA); in mgag200_pixpll_update_g200wb()423 tmp = RREG8(DAC_DATA); in mgag200_pixpll_update_g200wb()429 tmp = RREG8(DAC_DATA); in mgag200_pixpll_update_g200wb()436 tmp = RREG8(MGAREG_SEQ_DATA); in mgag200_pixpll_update_g200wb()[all …]
36 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg)) macro50 ((v) = RREG8(MGA_MISC_IN))64 RREG8(0x1fda); \72 v = RREG8(MGAREG_SEQ_DATA); \84 v = RREG8(MGAREG_CRTC_DATA); \96 v = RREG8(MGAREG_CRTCEXT_DATA); \
109 status = RREG8(MGAREG_Status + 2); in mga_wait_busy()122 tmp = RREG8(DAC_DATA); in mgag200_g200wb_hold_bmc()128 tmp = RREG8(DAC_DATA); in mgag200_g200wb_hold_bmc()136 tmp = RREG8(DAC_DATA); in mgag200_g200wb_hold_bmc()146 tmp = RREG8(DAC_DATA); in mgag200_g200wb_hold_bmc()159 tmp = RREG8(DAC_DATA); in mgag200_g200wb_hold_bmc()172 tmp = RREG8(MGAREG_CRTCEXT_DATA); in mgag200_g200wb_release_bmc()177 tmp = RREG8(DAC_DATA); in mgag200_g200wb_release_bmc()191 tmp = RREG8(DAC_DATA); in mgag200_g200wb_release_bmc()197 tmp = RREG8(DAC_DATA); in mgag200_g200wb_release_bmc()[all …]
39 return RREG8(DAC_DATA); in mga_i2c_read_gpio()47 tmp = (RREG8(DAC_DATA) & mask) | val; in mga_i2c_set_gpio()
101 misc = RREG8(MGA_MISC_IN); in mgag200_mm_init()
77 return RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2; in xgpu_ai_peek_ack()86 reg = RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE); in xgpu_ai_poll_ack()
75 return RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2; in xgpu_nv_peek_ack()84 reg = RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE); in xgpu_nv_poll_ack()
1170 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) macro
293 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) in radeon_wait_pll_lock()
3776 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); in r100_mc_stop()3829 tmp = RREG8(R_0003C2_GENMO_WT); in r100_vga_render_disable()
2541 #define RREG8(reg) readb((rdev->rmmio) + (reg)) macro
1146 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_legacy_get_lvds_info_from_regs()