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Searched refs:RREG32_NO_KIQ (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c323 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
328 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
337 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
345 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid()
356 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0); in xgpu_vi_mailbox_trans_msg()
372 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg()
377 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_vi_mailbox_rcv_msg()
393 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
403 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
502 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_vi_set_mailbox_ack_irq()
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Dmxgpu_ai.c56 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_peek_msg()
66 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_rcv_msg()
138 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_trans_msg()
180 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_send_access_requests()
236 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq()
287 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_rcv_irq()
Dmxgpu_nv.c55 return RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_nv_mailbox_peek_msg()
64 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_nv_mailbox_rcv_msg()
191 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1); in xgpu_nv_send_access_requests()
202 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2); in xgpu_nv_send_access_requests()
262 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_nv_set_mailbox_ack_irq()
319 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_nv_set_mailbox_rcv_irq()
Dvega10_ih.c350 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega10_ih_get_wptr()
366 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in vega10_ih_get_wptr()
391 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in vega10_ih_irq_rearm()
Dvega20_ih.c401 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega20_ih_get_wptr()
417 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in vega20_ih_get_wptr()
443 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in vega20_ih_irq_rearm()
Dnavi10_ih.c432 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in navi10_ih_get_wptr()
447 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in navi10_ih_get_wptr()
472 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in navi10_ih_irq_rearm()
Dvi.c305 (void)RREG32_NO_KIQ(mmPCIE_INDEX); in vi_pcie_rreg()
306 r = RREG32_NO_KIQ(mmPCIE_DATA); in vi_pcie_rreg()
317 (void)RREG32_NO_KIQ(mmPCIE_INDEX); in vi_pcie_wreg()
319 (void)RREG32_NO_KIQ(mmPCIE_DATA); in vi_pcie_wreg()
330 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); in vi_smc_rreg()
Dgmc_v9_0.c790 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + in gmc_v9_0_flush_gpu_tlb()
812 RREG32_NO_KIQ(hub->vm_inv_eng0_req + in gmc_v9_0_flush_gpu_tlb()
816 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + in gmc_v9_0_flush_gpu_tlb()
Damdgpu_virt.c45 return RREG32_NO_KIQ(0xc040) == 0xffffffff; in amdgpu_virt_mmio_blocked()
Damdgpu.h1164 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) macro
Damdgpu_device.c325 *data++ = RREG32_NO_KIQ(mmMM_DATA); in amdgpu_device_mm_access()
Dgfx_v10_0.c1617 return RREG32_NO_KIQ(offset); in gfx_v10_sriov_rreg()
8276 data = RREG32_NO_KIQ(reg); in gfx_v10_0_update_spm_vmid()
Dgfx_v8_0.c5628 data = RREG32_NO_KIQ(mmRLC_SPM_VMID); in gfx_v8_0_update_spm_vmid()
Dgfx_v9_0.c5099 data = RREG32_NO_KIQ(reg); in gfx_v9_0_update_spm_vmid()