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Searched refs:RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_sh_mask.h11509 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 macro
Ddce_11_0_sh_mask.h12617 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 macro
Ddce_10_0_sh_mask.h12611 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 macro
Ddce_11_2_sh_mask.h13233 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 macro
Ddce_12_0_sh_mask.h56087 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h27116 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
Ddcn_3_0_1_sh_mask.h230 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
Ddcn_1_0_sh_mask.h962 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
Ddcn_3_0_2_sh_mask.h54160 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
Ddcn_2_0_0_sh_mask.h59159 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
Ddcn_3_0_0_sh_mask.h62735 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro