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Searched refs:RING_MI_MODE (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Dmmio_context.c71 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
125 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
Dhandlers.c2237 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, in init_generic_mmio_info()
/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dintel_engine_cs.c1088 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); in __intel_engine_stop_cs()
1134 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in intel_engine_cancel_stop_cs()
1243 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) in ring_is_idle()
1487 ENGINE_READ(engine, RING_MI_MODE), in intel_engine_print_registers()
1488 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); in intel_engine_print_registers()
Dintel_ring_submission.c113 GEM_DEBUG_WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); in flush_cs_tlb()
238 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in xcs_resume()
1044 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); in ring_release()
Dintel_execlists_submission.c1966 ENGINE_READ(engine, RING_MI_MODE)); in process_csb()
2853 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in enable_execlists()
Dselftest_lrc.c285 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), in live_lrc_fixed()
/Linux-v5.15/drivers/gpu/drm/i915/
Di915_pmu.c321 val = ENGINE_READ_FW(engine, RING_MI_MODE); in engine_sample()
Di915_gpu_error.c1168 ee->mode = ENGINE_READ(engine, RING_MI_MODE); in engine_record_registers()
Di915_reg.h2715 #define RING_MI_MODE(base) _MMIO((base) + 0x9c) macro
/Linux-v5.15/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_submission.c2330 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in start_engine()
2331 ENGINE_POSTING_READ(engine, RING_MI_MODE); in start_engine()