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Searched refs:RING_IMR (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dgen6_engine_cs.c426 ENGINE_WRITE(engine, RING_IMR, in gen6_irq_enable()
430 ENGINE_POSTING_READ(engine, RING_IMR); in gen6_irq_enable()
437 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); in gen6_irq_disable()
443 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); in hsw_irq_enable_vecs()
446 ENGINE_POSTING_READ(engine, RING_IMR); in hsw_irq_enable_vecs()
453 ENGINE_WRITE(engine, RING_IMR, ~0); in hsw_irq_disable_vecs()
Dgen2_engine_cs.c297 ENGINE_POSTING_READ16(engine, RING_IMR); in gen2_irq_enable()
Dintel_execlists_submission.c3160 ENGINE_WRITE(engine, RING_IMR, in gen8_logical_ring_enable_irq()
3162 ENGINE_POSTING_READ(engine, RING_IMR); in gen8_logical_ring_enable_irq()
3167 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); in gen8_logical_ring_disable_irq()
Dintel_engine_cs.c1493 ENGINE_READ(engine, RING_IMR)); in intel_engine_print_registers()
/Linux-v5.15/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_ads.c256 GUC_MMIO_REG_ADD(regset, RING_IMR(base), false); in guc_mmio_regset_init()
/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Dhandlers.c2188 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, in init_generic_mmio_info()
/Linux-v5.15/drivers/gpu/drm/i915/
Di915_reg.h2617 #define RING_IMR(base) _MMIO((base) + 0xa8) macro