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Searched refs:RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_sh_mask.h11508 #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 macro
Ddce_11_0_sh_mask.h12616 #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 macro
Ddce_10_0_sh_mask.h12610 #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 macro
Ddce_11_2_sh_mask.h13232 #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 macro
Ddce_12_0_sh_mask.h56081 #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT … macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h27110 #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT … macro
Ddcn_3_0_1_sh_mask.h224 #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT … macro
Ddcn_1_0_sh_mask.h956 #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT … macro
Ddcn_3_0_2_sh_mask.h54154 #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT … macro
Ddcn_2_0_0_sh_mask.h59153 #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT … macro
Ddcn_3_0_0_sh_mask.h62729 #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT … macro