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Searched refs:RENDER_RING_BASE (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Dmmio_context.c51 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
52 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
53 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
54 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
55 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
56 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
57 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
58 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
59 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
60 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
[all …]
Dhandlers.c2160 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
2220 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); in init_generic_mmio_info()
3614 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
/Linux-v5.15/drivers/gpu/drm/i915/
Dintel_uncore.c953 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
963 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
964 RING_EXECLIST_CONTROL(RENDER_RING_BASE), /* 0x2550 */
985 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
986 RING_EXECLIST_CONTROL(RENDER_RING_BASE), /* 0x2550 */
1007 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
1008 RING_EXECLIST_CONTROL(RENDER_RING_BASE), /* 0x2550 */
2288 .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
2289 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
Di915_cmd_parser.c607 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
665 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
672 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
Di915_reg.h2510 #define RENDER_RING_BASE 0x02000 macro
2536 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2537 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2538 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dintel_gt.c274 clear_register(uncore, IPEIR(RENDER_RING_BASE)); in intel_gt_clear_error_registers()
421 RING_HEAD(RENDER_RING_BASE)); in intel_gt_flush_ggtt_writes()
Dintel_engine_cs.c58 { .graphics_ver = 1, .base = RENDER_RING_BASE }