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Searched refs:REG_GET_FIELD (Results 1 – 25 of 56) sorted by relevance

123

/Linux-v5.15/drivers/gpu/drm/amd/amdkfd/
Dkfd_int_process_v9.c193 encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING); in event_interrupt_wq_v9()
198 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, SE_ID), in event_interrupt_wq_v9()
199 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE), in event_interrupt_wq_v9()
200 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, WLT), in event_interrupt_wq_v9()
201 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_BUF_FULL), in event_interrupt_wq_v9()
202 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, REG_TIMESTAMP), in event_interrupt_wq_v9()
203 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, CMD_TIMESTAMP), in event_interrupt_wq_v9()
204 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_CMD_OVERFLOW), in event_interrupt_wq_v9()
205 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_REG_OVERFLOW), in event_interrupt_wq_v9()
206 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, IMMED_OVERFLOW), in event_interrupt_wq_v9()
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/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dumc_v6_7.c78 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_7_query_correctable_error_count()
88 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_7_query_correctable_error_count()
94 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_7_query_correctable_error_count()
95 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v6_7_query_correctable_error_count()
111 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v6_7_querry_uncorrectable_error_count()
112 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v6_7_querry_uncorrectable_error_count()
113 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v6_7_querry_uncorrectable_error_count()
114 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v6_7_querry_uncorrectable_error_count()
115 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v6_7_querry_uncorrectable_error_count()
116 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v6_7_querry_uncorrectable_error_count()
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Dumc_v8_7.c129 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) - in umc_v8_7_query_correctable_error_count()
139 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) - in umc_v8_7_query_correctable_error_count()
145 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && in umc_v8_7_query_correctable_error_count()
146 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_7_query_correctable_error_count()
147 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v8_7_query_correctable_error_count()
162 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v8_7_querry_uncorrectable_error_count()
163 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v8_7_querry_uncorrectable_error_count()
164 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v8_7_querry_uncorrectable_error_count()
165 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v8_7_querry_uncorrectable_error_count()
166 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v8_7_querry_uncorrectable_error_count()
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Damdgpu_mca.c36 if (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in amdgpu_mca_query_correctable_error_count()
37 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in amdgpu_mca_query_correctable_error_count()
47 if ((REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in amdgpu_mca_query_uncorrectable_error_count()
48 (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
49 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
50 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
51 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
52 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in amdgpu_mca_query_uncorrectable_error_count()
Dumc_v6_1.c82 return REG_GET_FIELD(rsmu_umc_val, in umc_v6_1_get_umc_index_mode_state()
204 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_1_query_correctable_error_count()
214 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_1_query_correctable_error_count()
220 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && in umc_v6_1_query_correctable_error_count()
221 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_1_query_correctable_error_count()
222 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v6_1_query_correctable_error_count()
245 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v6_1_querry_uncorrectable_error_count()
246 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
247 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
248 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
[all …]
Dgfxhub_v1_1.c54 seg_size = REG_GET_FIELD( in gfxhub_v1_1_get_xgmi_info()
59 seg_size = REG_GET_FIELD( in gfxhub_v1_1_get_xgmi_info()
65 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); in gfxhub_v1_1_get_xgmi_info()
93 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, in gfxhub_v1_1_get_xgmi_info()
Dsmu_v11_0_i2c.c89 if (REG_GET_FIELD(en_stat, CKSVII2C_IC_ENABLE_STATUS, IC_EN)) in smu_v11_0_i2c_enable()
183 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0); in smu_v11_0_i2c_poll_tx_status()
191 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { in smu_v11_0_i2c_poll_tx_status()
196 if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_tx_status()
202 } else if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_tx_status()
226 if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_rx_status()
244 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0); in smu_v11_0_i2c_poll_rx_status()
291 if (!REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) { in smu_v11_0_i2c_transmit()
414 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT); in smu_v11_0_i2c_receive()
459 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && in smu_v11_0_i2c_activity_done()
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Dsmuio_v13_0.c86 die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID); in smuio_v13_0_get_die_id()
103 socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID); in smuio_v13_0_get_socket_id()
120 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID); in smuio_v13_0_is_host_gpu_xgmi_supported()
Dgfxhub_v2_1.c82 u32 cid = REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
92 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
95 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
98 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
101 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
104 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
505 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); in gfxhub_v2_1_get_xgmi_info()
525 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); in gfxhub_v2_1_get_xgmi_info()
529 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( in gfxhub_v2_1_get_xgmi_info()
Dgmc_v7_0.c97 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v7_0_mc_stop()
203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v7_0_mc_init()
339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v7_0_mc_init()
778 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v7_0_vm_decode_fault()
779 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
785 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
790 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
[all …]
Dgfx_v9_4.c711 sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT); in gfx_v9_4_query_utc_edc_status()
719 ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT); in gfx_v9_4_query_utc_edc_status()
732 sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
741 ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
755 sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT); in gfx_v9_4_query_utc_edc_status()
763 ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT); in gfx_v9_4_query_utc_edc_status()
776 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
785 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
799 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
808 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
[all …]
Dgmc_v8_0.c186 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v8_0_mc_stop()
319 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
342 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
348 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
526 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v8_0_mc_init()
532 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v8_0_mc_init()
1012 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v8_0_vm_decode_fault()
1013 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
1019 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
1024 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
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Dgfxhub_v2_0.c79 u32 cid = REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
89 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
92 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
95 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
98 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
101 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
Dcz_ih.c197 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
350 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_is_idle()
365 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_wait_for_idle()
Diceland_ih.c197 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
349 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_is_idle()
364 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_wait_for_idle()
Dgmc_v6_0.c71 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v6_0_mc_stop()
618 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v6_0_vm_decode_fault()
619 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
624 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
629 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
806 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v6_0_get_vbios_fb_size()
810 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v6_0_get_vbios_fb_size()
811 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * in gmc_v6_0_get_vbios_fb_size()
Dtonga_ih.c199 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
205 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
361 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in tonga_ih_is_idle()
376 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in tonga_ih_wait_for_idle()
Dgmc_v9_0.c586 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); in gmc_v9_0_process_interrupt()
587 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); in gmc_v9_0_process_interrupt()
630 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
633 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
636 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
639 REG_GET_FIELD(status, in gmc_v9_0_process_interrupt()
1106 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v9_0_get_vbios_fb_size()
1115 size = (REG_GET_FIELD(viewport, in gmc_v9_0_get_vbios_fb_size()
1117 REG_GET_FIELD(viewport, in gmc_v9_0_get_vbios_fb_size()
1126 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v9_0_get_vbios_fb_size()
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Dnbio_v7_4.c362 if (REG_GET_FIELD(bif_doorbell_intr_cntl, in nbio_v7_4_handle_ras_controller_intr_no_bifring()
418 if (REG_GET_FIELD(bif_doorbell_intr_cntl, in nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring()
579 corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr); in nbio_v7_4_query_ras_error_count()
580 fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal); in nbio_v7_4_query_ras_error_count()
581 non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, in nbio_v7_4_query_ras_error_count()
600 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS, in nbio_v7_4_query_ras_error_count()
Dmmhub_v2_0.c148 cid = REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
150 rw = REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
177 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
180 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
183 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
186 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
Dmmhub_v2_3.c85 cid = REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
87 rw = REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
105 REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
108 REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
111 REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
114 REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
Damdgpu_amdkfd_gfx_v7.c455 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
459 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
460 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
467 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
685 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in read_vmid_from_vmfault_reg()
Dgfx_v8_0.c1839 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1841 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1849 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v8_0_gpu_early_init()
1850 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v8_0_gpu_early_init()
1853 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v8_0_gpu_early_init()
1854 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v8_0_gpu_early_init()
1873 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); in gfx_v8_0_gpu_early_init()
3475 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); in gfx_v8_0_get_rb_active_bitmap()
4883 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE) in gfx_v8_0_is_idle()
4995 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) in gfx_v8_0_check_soft_reset()
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega20_thermal.c124 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_get_fan_speed_pwm()
126 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), in vega20_fan_ctrl_get_fan_speed_pwm()
152 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_set_fan_speed_pwm()
Dvega10_thermal.c105 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
133 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
136 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
264 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_set_fan_speed_pwm()

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