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Searched refs:REG_FIELD_MASK (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c321 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); in xgpu_vi_mailbox_send_ack()
368 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); in xgpu_vi_mailbox_rcv_msg()
390 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK); in xgpu_vi_poll_ack()
Dsoc15_common.h45 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
180 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
Damdgpu.h1224 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK macro
1227 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1228 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1231 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1234 …WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, fi…
1237 …WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_F…
/Linux-v5.15/drivers/misc/habanalabs/common/
Dhabanalabs.h2038 #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK macro
2041 ~REG_FIELD_MASK(reg, field)) | \