Searched refs:REG_BIT (Results 1 – 6 of 6) sorted by relevance
142 #define SLPC_GTPERF_TASK_ENABLED REG_BIT(0)143 #define SLPC_DCC_TASK_ENABLED REG_BIT(11)144 #define SLPC_IN_DCC REG_BIT(12)145 #define SLPC_BALANCER_ENABLED REG_BIT(15)146 #define SLPC_IBC_TASK_ENABLED REG_BIT(16)147 #define SLPC_BALANCER_IA_LMT_ENABLED REG_BIT(17)148 #define SLPC_BALANCER_IA_LMT_ACTIVE REG_BIT(18)
61 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)62 #define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)63 #define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)64 #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)65 #define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)69 #define EL_CTRL_LOAD REG_BIT(0)
129 #define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21))142 #define MI_LRI_LRM_CS_MMIO REG_BIT(19)160 #define MI_LRR_SOURCE_CS_MMIO REG_BIT(18)170 #define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)171 #define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/241 #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */298 #define BASE_ADDRESS_MODIFY REG_BIT(0)301 #define PIPELINE_SELECT_MEDIA REG_BIT(0)
74 #define GEN6_PTE_VALID REG_BIT(0)80 #define GEN6_PDE_VALID REG_BIT(0)85 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)86 #define BYT_PTE_WRITEABLE REG_BIT(1)126 #define CHV_PPAT_SNOOP REG_BIT(6)
298 *cs++ = MI_STORE_DATA_IMM | REG_BIT(21); /* as qword elements */ in emit_pte()319 *cs++ = MI_STORE_DATA_IMM | REG_BIT(21); in emit_pte()
127 #define REG_BIT(__n) \ macro428 #define GEN12_HCP_SFC_FORCED_LOCK_BIT REG_BIT(0)430 #define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1)431 #define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0)505 #define LMEM_INIT REG_BIT(7)584 #define BCS_SRC_Y REG_BIT(0)585 #define BCS_DST_Y REG_BIT(1)2035 #define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)2041 #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)2239 #define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)[all …]
