1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Driver for Renesas R-Car MIPI CSI-2 Receiver
4  *
5  * Copyright (C) 2018 Renesas Electronics Corp.
6  */
7 
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/reset.h>
18 #include <linux/sys_soc.h>
19 
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-mc.h>
24 #include <media/v4l2-subdev.h>
25 
26 struct rcar_csi2;
27 
28 /* Register offsets and bits */
29 
30 /* Control Timing Select */
31 #define TREF_REG			0x00
32 #define TREF_TREF			BIT(0)
33 
34 /* Software Reset */
35 #define SRST_REG			0x04
36 #define SRST_SRST			BIT(0)
37 
38 /* PHY Operation Control */
39 #define PHYCNT_REG			0x08
40 #define PHYCNT_SHUTDOWNZ		BIT(17)
41 #define PHYCNT_RSTZ			BIT(16)
42 #define PHYCNT_ENABLECLK		BIT(4)
43 #define PHYCNT_ENABLE_3			BIT(3)
44 #define PHYCNT_ENABLE_2			BIT(2)
45 #define PHYCNT_ENABLE_1			BIT(1)
46 #define PHYCNT_ENABLE_0			BIT(0)
47 
48 /* Checksum Control */
49 #define CHKSUM_REG			0x0c
50 #define CHKSUM_ECC_EN			BIT(1)
51 #define CHKSUM_CRC_EN			BIT(0)
52 
53 /*
54  * Channel Data Type Select
55  * VCDT[0-15]:  Channel 0 VCDT[16-31]:  Channel 1
56  * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3
57  */
58 #define VCDT_REG			0x10
59 #define VCDT2_REG			0x14
60 #define VCDT_VCDTN_EN			BIT(15)
61 #define VCDT_SEL_VC(n)			(((n) & 0x3) << 8)
62 #define VCDT_SEL_DTN_ON			BIT(6)
63 #define VCDT_SEL_DT(n)			(((n) & 0x3f) << 0)
64 
65 /* Frame Data Type Select */
66 #define FRDT_REG			0x18
67 
68 /* Field Detection Control */
69 #define FLD_REG				0x1c
70 #define FLD_FLD_NUM(n)			(((n) & 0xff) << 16)
71 #define FLD_DET_SEL(n)			(((n) & 0x3) << 4)
72 #define FLD_FLD_EN4			BIT(3)
73 #define FLD_FLD_EN3			BIT(2)
74 #define FLD_FLD_EN2			BIT(1)
75 #define FLD_FLD_EN			BIT(0)
76 
77 /* Automatic Standby Control */
78 #define ASTBY_REG			0x20
79 
80 /* Long Data Type Setting 0 */
81 #define LNGDT0_REG			0x28
82 
83 /* Long Data Type Setting 1 */
84 #define LNGDT1_REG			0x2c
85 
86 /* Interrupt Enable */
87 #define INTEN_REG			0x30
88 #define INTEN_INT_AFIFO_OF		BIT(27)
89 #define INTEN_INT_ERRSOTHS		BIT(4)
90 #define INTEN_INT_ERRSOTSYNCHS		BIT(3)
91 
92 /* Interrupt Source Mask */
93 #define INTCLOSE_REG			0x34
94 
95 /* Interrupt Status Monitor */
96 #define INTSTATE_REG			0x38
97 #define INTSTATE_INT_ULPS_START		BIT(7)
98 #define INTSTATE_INT_ULPS_END		BIT(6)
99 
100 /* Interrupt Error Status Monitor */
101 #define INTERRSTATE_REG			0x3c
102 
103 /* Short Packet Data */
104 #define SHPDAT_REG			0x40
105 
106 /* Short Packet Count */
107 #define SHPCNT_REG			0x44
108 
109 /* LINK Operation Control */
110 #define LINKCNT_REG			0x48
111 #define LINKCNT_MONITOR_EN		BIT(31)
112 #define LINKCNT_REG_MONI_PACT_EN	BIT(25)
113 #define LINKCNT_ICLK_NONSTOP		BIT(24)
114 
115 /* Lane Swap */
116 #define LSWAP_REG			0x4c
117 #define LSWAP_L3SEL(n)			(((n) & 0x3) << 6)
118 #define LSWAP_L2SEL(n)			(((n) & 0x3) << 4)
119 #define LSWAP_L1SEL(n)			(((n) & 0x3) << 2)
120 #define LSWAP_L0SEL(n)			(((n) & 0x3) << 0)
121 
122 /* PHY Test Interface Write Register */
123 #define PHTW_REG			0x50
124 #define PHTW_DWEN			BIT(24)
125 #define PHTW_TESTDIN_DATA(n)		(((n & 0xff)) << 16)
126 #define PHTW_CWEN			BIT(8)
127 #define PHTW_TESTDIN_CODE(n)		((n & 0xff))
128 
129 struct phtw_value {
130 	u16 data;
131 	u16 code;
132 };
133 
134 struct rcsi2_mbps_reg {
135 	u16 mbps;
136 	u16 reg;
137 };
138 
139 static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = {
140 	{ .mbps =   80, .reg = 0x86 },
141 	{ .mbps =   90, .reg = 0x86 },
142 	{ .mbps =  100, .reg = 0x87 },
143 	{ .mbps =  110, .reg = 0x87 },
144 	{ .mbps =  120, .reg = 0x88 },
145 	{ .mbps =  130, .reg = 0x88 },
146 	{ .mbps =  140, .reg = 0x89 },
147 	{ .mbps =  150, .reg = 0x89 },
148 	{ .mbps =  160, .reg = 0x8a },
149 	{ .mbps =  170, .reg = 0x8a },
150 	{ .mbps =  180, .reg = 0x8b },
151 	{ .mbps =  190, .reg = 0x8b },
152 	{ .mbps =  205, .reg = 0x8c },
153 	{ .mbps =  220, .reg = 0x8d },
154 	{ .mbps =  235, .reg = 0x8e },
155 	{ .mbps =  250, .reg = 0x8e },
156 	{ /* sentinel */ },
157 };
158 
159 static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = {
160 	{ .mbps =   80, .reg = 0x00 },
161 	{ .mbps =   90, .reg = 0x20 },
162 	{ .mbps =  100, .reg = 0x40 },
163 	{ .mbps =  110, .reg = 0x02 },
164 	{ .mbps =  130, .reg = 0x22 },
165 	{ .mbps =  140, .reg = 0x42 },
166 	{ .mbps =  150, .reg = 0x04 },
167 	{ .mbps =  170, .reg = 0x24 },
168 	{ .mbps =  180, .reg = 0x44 },
169 	{ .mbps =  200, .reg = 0x06 },
170 	{ .mbps =  220, .reg = 0x26 },
171 	{ .mbps =  240, .reg = 0x46 },
172 	{ .mbps =  250, .reg = 0x08 },
173 	{ .mbps =  270, .reg = 0x28 },
174 	{ .mbps =  300, .reg = 0x0a },
175 	{ .mbps =  330, .reg = 0x2a },
176 	{ .mbps =  360, .reg = 0x4a },
177 	{ .mbps =  400, .reg = 0x0c },
178 	{ .mbps =  450, .reg = 0x2c },
179 	{ .mbps =  500, .reg = 0x0e },
180 	{ .mbps =  550, .reg = 0x2e },
181 	{ .mbps =  600, .reg = 0x10 },
182 	{ .mbps =  650, .reg = 0x30 },
183 	{ .mbps =  700, .reg = 0x12 },
184 	{ .mbps =  750, .reg = 0x32 },
185 	{ .mbps =  800, .reg = 0x52 },
186 	{ .mbps =  850, .reg = 0x72 },
187 	{ .mbps =  900, .reg = 0x14 },
188 	{ .mbps =  950, .reg = 0x34 },
189 	{ .mbps = 1000, .reg = 0x54 },
190 	{ .mbps = 1050, .reg = 0x74 },
191 	{ .mbps = 1125, .reg = 0x16 },
192 	{ /* sentinel */ },
193 };
194 
195 /* PHY Test Interface Clear */
196 #define PHTC_REG			0x58
197 #define PHTC_TESTCLR			BIT(0)
198 
199 /* PHY Frequency Control */
200 #define PHYPLL_REG			0x68
201 #define PHYPLL_HSFREQRANGE(n)		((n) << 16)
202 
203 static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = {
204 	{ .mbps =   80, .reg = 0x00 },
205 	{ .mbps =   90, .reg = 0x10 },
206 	{ .mbps =  100, .reg = 0x20 },
207 	{ .mbps =  110, .reg = 0x30 },
208 	{ .mbps =  120, .reg = 0x01 },
209 	{ .mbps =  130, .reg = 0x11 },
210 	{ .mbps =  140, .reg = 0x21 },
211 	{ .mbps =  150, .reg = 0x31 },
212 	{ .mbps =  160, .reg = 0x02 },
213 	{ .mbps =  170, .reg = 0x12 },
214 	{ .mbps =  180, .reg = 0x22 },
215 	{ .mbps =  190, .reg = 0x32 },
216 	{ .mbps =  205, .reg = 0x03 },
217 	{ .mbps =  220, .reg = 0x13 },
218 	{ .mbps =  235, .reg = 0x23 },
219 	{ .mbps =  250, .reg = 0x33 },
220 	{ .mbps =  275, .reg = 0x04 },
221 	{ .mbps =  300, .reg = 0x14 },
222 	{ .mbps =  325, .reg = 0x25 },
223 	{ .mbps =  350, .reg = 0x35 },
224 	{ .mbps =  400, .reg = 0x05 },
225 	{ .mbps =  450, .reg = 0x16 },
226 	{ .mbps =  500, .reg = 0x26 },
227 	{ .mbps =  550, .reg = 0x37 },
228 	{ .mbps =  600, .reg = 0x07 },
229 	{ .mbps =  650, .reg = 0x18 },
230 	{ .mbps =  700, .reg = 0x28 },
231 	{ .mbps =  750, .reg = 0x39 },
232 	{ .mbps =  800, .reg = 0x09 },
233 	{ .mbps =  850, .reg = 0x19 },
234 	{ .mbps =  900, .reg = 0x29 },
235 	{ .mbps =  950, .reg = 0x3a },
236 	{ .mbps = 1000, .reg = 0x0a },
237 	{ .mbps = 1050, .reg = 0x1a },
238 	{ .mbps = 1100, .reg = 0x2a },
239 	{ .mbps = 1150, .reg = 0x3b },
240 	{ .mbps = 1200, .reg = 0x0b },
241 	{ .mbps = 1250, .reg = 0x1b },
242 	{ .mbps = 1300, .reg = 0x2b },
243 	{ .mbps = 1350, .reg = 0x3c },
244 	{ .mbps = 1400, .reg = 0x0c },
245 	{ .mbps = 1450, .reg = 0x1c },
246 	{ .mbps = 1500, .reg = 0x2c },
247 	{ /* sentinel */ },
248 };
249 
250 static const struct rcsi2_mbps_reg hsfreqrange_m3w_h3es1[] = {
251 	{ .mbps =   80,	.reg = 0x00 },
252 	{ .mbps =   90,	.reg = 0x10 },
253 	{ .mbps =  100,	.reg = 0x20 },
254 	{ .mbps =  110,	.reg = 0x30 },
255 	{ .mbps =  120,	.reg = 0x01 },
256 	{ .mbps =  130,	.reg = 0x11 },
257 	{ .mbps =  140,	.reg = 0x21 },
258 	{ .mbps =  150,	.reg = 0x31 },
259 	{ .mbps =  160,	.reg = 0x02 },
260 	{ .mbps =  170,	.reg = 0x12 },
261 	{ .mbps =  180,	.reg = 0x22 },
262 	{ .mbps =  190,	.reg = 0x32 },
263 	{ .mbps =  205,	.reg = 0x03 },
264 	{ .mbps =  220,	.reg = 0x13 },
265 	{ .mbps =  235,	.reg = 0x23 },
266 	{ .mbps =  250,	.reg = 0x33 },
267 	{ .mbps =  275,	.reg = 0x04 },
268 	{ .mbps =  300,	.reg = 0x14 },
269 	{ .mbps =  325,	.reg = 0x05 },
270 	{ .mbps =  350,	.reg = 0x15 },
271 	{ .mbps =  400,	.reg = 0x25 },
272 	{ .mbps =  450,	.reg = 0x06 },
273 	{ .mbps =  500,	.reg = 0x16 },
274 	{ .mbps =  550,	.reg = 0x07 },
275 	{ .mbps =  600,	.reg = 0x17 },
276 	{ .mbps =  650,	.reg = 0x08 },
277 	{ .mbps =  700,	.reg = 0x18 },
278 	{ .mbps =  750,	.reg = 0x09 },
279 	{ .mbps =  800,	.reg = 0x19 },
280 	{ .mbps =  850,	.reg = 0x29 },
281 	{ .mbps =  900,	.reg = 0x39 },
282 	{ .mbps =  950,	.reg = 0x0a },
283 	{ .mbps = 1000,	.reg = 0x1a },
284 	{ .mbps = 1050,	.reg = 0x2a },
285 	{ .mbps = 1100,	.reg = 0x3a },
286 	{ .mbps = 1150,	.reg = 0x0b },
287 	{ .mbps = 1200,	.reg = 0x1b },
288 	{ .mbps = 1250,	.reg = 0x2b },
289 	{ .mbps = 1300,	.reg = 0x3b },
290 	{ .mbps = 1350,	.reg = 0x0c },
291 	{ .mbps = 1400,	.reg = 0x1c },
292 	{ .mbps = 1450,	.reg = 0x2c },
293 	{ .mbps = 1500,	.reg = 0x3c },
294 	{ /* sentinel */ },
295 };
296 
297 /* PHY ESC Error Monitor */
298 #define PHEERM_REG			0x74
299 
300 /* PHY Clock Lane Monitor */
301 #define PHCLM_REG			0x78
302 #define PHCLM_STOPSTATECKL		BIT(0)
303 
304 /* PHY Data Lane Monitor */
305 #define PHDLM_REG			0x7c
306 
307 /* CSI0CLK Frequency Configuration Preset Register */
308 #define CSI0CLKFCPR_REG			0x260
309 #define CSI0CLKFREQRANGE(n)		((n & 0x3f) << 16)
310 
311 struct rcar_csi2_format {
312 	u32 code;
313 	unsigned int datatype;
314 	unsigned int bpp;
315 };
316 
317 static const struct rcar_csi2_format rcar_csi2_formats[] = {
318 	{ .code = MEDIA_BUS_FMT_RGB888_1X24,	.datatype = 0x24, .bpp = 24 },
319 	{ .code = MEDIA_BUS_FMT_UYVY8_1X16,	.datatype = 0x1e, .bpp = 16 },
320 	{ .code = MEDIA_BUS_FMT_YUYV8_1X16,	.datatype = 0x1e, .bpp = 16 },
321 	{ .code = MEDIA_BUS_FMT_UYVY8_2X8,	.datatype = 0x1e, .bpp = 16 },
322 	{ .code = MEDIA_BUS_FMT_YUYV10_2X10,	.datatype = 0x1e, .bpp = 20 },
323 	{ .code = MEDIA_BUS_FMT_Y10_1X10,	.datatype = 0x2b, .bpp = 10 },
324 	{ .code = MEDIA_BUS_FMT_SBGGR8_1X8,     .datatype = 0x2a, .bpp = 8 },
325 	{ .code = MEDIA_BUS_FMT_SGBRG8_1X8,     .datatype = 0x2a, .bpp = 8 },
326 	{ .code = MEDIA_BUS_FMT_SGRBG8_1X8,     .datatype = 0x2a, .bpp = 8 },
327 	{ .code = MEDIA_BUS_FMT_SRGGB8_1X8,     .datatype = 0x2a, .bpp = 8 },
328 	{ .code = MEDIA_BUS_FMT_Y8_1X8,		.datatype = 0x2a, .bpp = 8 },
329 };
330 
rcsi2_code_to_fmt(unsigned int code)331 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)
332 {
333 	unsigned int i;
334 
335 	for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++)
336 		if (rcar_csi2_formats[i].code == code)
337 			return &rcar_csi2_formats[i];
338 
339 	return NULL;
340 }
341 
342 enum rcar_csi2_pads {
343 	RCAR_CSI2_SINK,
344 	RCAR_CSI2_SOURCE_VC0,
345 	RCAR_CSI2_SOURCE_VC1,
346 	RCAR_CSI2_SOURCE_VC2,
347 	RCAR_CSI2_SOURCE_VC3,
348 	NR_OF_RCAR_CSI2_PAD,
349 };
350 
351 struct rcar_csi2_info {
352 	int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps);
353 	int (*phy_post_init)(struct rcar_csi2 *priv);
354 	const struct rcsi2_mbps_reg *hsfreqrange;
355 	unsigned int csi0clkfreqrange;
356 	unsigned int num_channels;
357 	bool clear_ulps;
358 };
359 
360 struct rcar_csi2 {
361 	struct device *dev;
362 	void __iomem *base;
363 	const struct rcar_csi2_info *info;
364 	struct reset_control *rstc;
365 
366 	struct v4l2_subdev subdev;
367 	struct media_pad pads[NR_OF_RCAR_CSI2_PAD];
368 
369 	struct v4l2_async_notifier notifier;
370 	struct v4l2_subdev *remote;
371 	unsigned int remote_pad;
372 
373 	struct v4l2_mbus_framefmt mf;
374 
375 	struct mutex lock;
376 	int stream_count;
377 
378 	unsigned short lanes;
379 	unsigned char lane_swap[4];
380 };
381 
sd_to_csi2(struct v4l2_subdev * sd)382 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
383 {
384 	return container_of(sd, struct rcar_csi2, subdev);
385 }
386 
notifier_to_csi2(struct v4l2_async_notifier * n)387 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
388 {
389 	return container_of(n, struct rcar_csi2, notifier);
390 }
391 
rcsi2_read(struct rcar_csi2 * priv,unsigned int reg)392 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg)
393 {
394 	return ioread32(priv->base + reg);
395 }
396 
rcsi2_write(struct rcar_csi2 * priv,unsigned int reg,u32 data)397 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)
398 {
399 	iowrite32(data, priv->base + reg);
400 }
401 
rcsi2_enter_standby(struct rcar_csi2 * priv)402 static void rcsi2_enter_standby(struct rcar_csi2 *priv)
403 {
404 	rcsi2_write(priv, PHYCNT_REG, 0);
405 	rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR);
406 	reset_control_assert(priv->rstc);
407 	usleep_range(100, 150);
408 	pm_runtime_put(priv->dev);
409 }
410 
rcsi2_exit_standby(struct rcar_csi2 * priv)411 static int rcsi2_exit_standby(struct rcar_csi2 *priv)
412 {
413 	int ret;
414 
415 	ret = pm_runtime_resume_and_get(priv->dev);
416 	if (ret < 0)
417 		return ret;
418 
419 	reset_control_deassert(priv->rstc);
420 
421 	return 0;
422 }
423 
rcsi2_wait_phy_start(struct rcar_csi2 * priv,unsigned int lanes)424 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv,
425 				unsigned int lanes)
426 {
427 	unsigned int timeout;
428 
429 	/* Wait for the clock and data lanes to enter LP-11 state. */
430 	for (timeout = 0; timeout <= 20; timeout++) {
431 		const u32 lane_mask = (1 << lanes) - 1;
432 
433 		if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL)  &&
434 		    (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask)
435 			return 0;
436 
437 		usleep_range(1000, 2000);
438 	}
439 
440 	dev_err(priv->dev, "Timeout waiting for LP-11 state\n");
441 
442 	return -ETIMEDOUT;
443 }
444 
rcsi2_set_phypll(struct rcar_csi2 * priv,unsigned int mbps)445 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps)
446 {
447 	const struct rcsi2_mbps_reg *hsfreq;
448 
449 	for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++)
450 		if (hsfreq->mbps >= mbps)
451 			break;
452 
453 	if (!hsfreq->mbps) {
454 		dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
455 		return -ERANGE;
456 	}
457 
458 	rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg));
459 
460 	return 0;
461 }
462 
rcsi2_calc_mbps(struct rcar_csi2 * priv,unsigned int bpp,unsigned int lanes)463 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp,
464 			   unsigned int lanes)
465 {
466 	struct v4l2_subdev *source;
467 	struct v4l2_ctrl *ctrl;
468 	u64 mbps;
469 
470 	if (!priv->remote)
471 		return -ENODEV;
472 
473 	source = priv->remote;
474 
475 	/* Read the pixel rate control from remote. */
476 	ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);
477 	if (!ctrl) {
478 		dev_err(priv->dev, "no pixel rate control in subdev %s\n",
479 			source->name);
480 		return -EINVAL;
481 	}
482 
483 	/*
484 	 * Calculate the phypll in mbps.
485 	 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes)
486 	 * bps = link_freq * 2
487 	 */
488 	mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp;
489 	do_div(mbps, lanes * 1000000);
490 
491 	return mbps;
492 }
493 
rcsi2_get_active_lanes(struct rcar_csi2 * priv,unsigned int * lanes)494 static int rcsi2_get_active_lanes(struct rcar_csi2 *priv,
495 				  unsigned int *lanes)
496 {
497 	struct v4l2_mbus_config mbus_config = { 0 };
498 	unsigned int num_lanes = UINT_MAX;
499 	int ret;
500 
501 	*lanes = priv->lanes;
502 
503 	ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config,
504 			       priv->remote_pad, &mbus_config);
505 	if (ret == -ENOIOCTLCMD) {
506 		dev_dbg(priv->dev, "No remote mbus configuration available\n");
507 		return 0;
508 	}
509 
510 	if (ret) {
511 		dev_err(priv->dev, "Failed to get remote mbus configuration\n");
512 		return ret;
513 	}
514 
515 	if (mbus_config.type != V4L2_MBUS_CSI2_DPHY) {
516 		dev_err(priv->dev, "Unsupported media bus type %u\n",
517 			mbus_config.type);
518 		return -EINVAL;
519 	}
520 
521 	if (mbus_config.flags & V4L2_MBUS_CSI2_1_LANE)
522 		num_lanes = 1;
523 	else if (mbus_config.flags & V4L2_MBUS_CSI2_2_LANE)
524 		num_lanes = 2;
525 	else if (mbus_config.flags & V4L2_MBUS_CSI2_3_LANE)
526 		num_lanes = 3;
527 	else if (mbus_config.flags & V4L2_MBUS_CSI2_4_LANE)
528 		num_lanes = 4;
529 
530 	if (num_lanes > priv->lanes) {
531 		dev_err(priv->dev,
532 			"Unsupported mbus config: too many data lanes %u\n",
533 			num_lanes);
534 		return -EINVAL;
535 	}
536 
537 	*lanes = num_lanes;
538 
539 	return 0;
540 }
541 
rcsi2_start_receiver(struct rcar_csi2 * priv)542 static int rcsi2_start_receiver(struct rcar_csi2 *priv)
543 {
544 	const struct rcar_csi2_format *format;
545 	u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0;
546 	unsigned int lanes;
547 	unsigned int i;
548 	int mbps, ret;
549 
550 	dev_dbg(priv->dev, "Input size (%ux%u%c)\n",
551 		priv->mf.width, priv->mf.height,
552 		priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i');
553 
554 	/* Code is validated in set_fmt. */
555 	format = rcsi2_code_to_fmt(priv->mf.code);
556 
557 	/*
558 	 * Enable all supported CSI-2 channels with virtual channel and
559 	 * data type matching.
560 	 *
561 	 * NOTE: It's not possible to get individual datatype for each
562 	 *       source virtual channel. Once this is possible in V4L2
563 	 *       it should be used here.
564 	 */
565 	for (i = 0; i < priv->info->num_channels; i++) {
566 		u32 vcdt_part;
567 
568 		vcdt_part = VCDT_SEL_VC(i) | VCDT_VCDTN_EN | VCDT_SEL_DTN_ON |
569 			VCDT_SEL_DT(format->datatype);
570 
571 		/* Store in correct reg and offset. */
572 		if (i < 2)
573 			vcdt |= vcdt_part << ((i % 2) * 16);
574 		else
575 			vcdt2 |= vcdt_part << ((i % 2) * 16);
576 	}
577 
578 	if (priv->mf.field == V4L2_FIELD_ALTERNATE) {
579 		fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2
580 			| FLD_FLD_EN;
581 
582 		if (priv->mf.height == 240)
583 			fld |= FLD_FLD_NUM(0);
584 		else
585 			fld |= FLD_FLD_NUM(1);
586 	}
587 
588 	/*
589 	 * Get the number of active data lanes inspecting the remote mbus
590 	 * configuration.
591 	 */
592 	ret = rcsi2_get_active_lanes(priv, &lanes);
593 	if (ret)
594 		return ret;
595 
596 	phycnt = PHYCNT_ENABLECLK;
597 	phycnt |= (1 << lanes) - 1;
598 
599 	mbps = rcsi2_calc_mbps(priv, format->bpp, lanes);
600 	if (mbps < 0)
601 		return mbps;
602 
603 	/* Enable interrupts. */
604 	rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS
605 		    | INTEN_INT_ERRSOTSYNCHS);
606 
607 	/* Init */
608 	rcsi2_write(priv, TREF_REG, TREF_TREF);
609 	rcsi2_write(priv, PHTC_REG, 0);
610 
611 	/* Configure */
612 	rcsi2_write(priv, VCDT_REG, vcdt);
613 	if (vcdt2)
614 		rcsi2_write(priv, VCDT2_REG, vcdt2);
615 	/* Lanes are zero indexed. */
616 	rcsi2_write(priv, LSWAP_REG,
617 		    LSWAP_L0SEL(priv->lane_swap[0] - 1) |
618 		    LSWAP_L1SEL(priv->lane_swap[1] - 1) |
619 		    LSWAP_L2SEL(priv->lane_swap[2] - 1) |
620 		    LSWAP_L3SEL(priv->lane_swap[3] - 1));
621 
622 	/* Start */
623 	if (priv->info->init_phtw) {
624 		ret = priv->info->init_phtw(priv, mbps);
625 		if (ret)
626 			return ret;
627 	}
628 
629 	if (priv->info->hsfreqrange) {
630 		ret = rcsi2_set_phypll(priv, mbps);
631 		if (ret)
632 			return ret;
633 	}
634 
635 	if (priv->info->csi0clkfreqrange)
636 		rcsi2_write(priv, CSI0CLKFCPR_REG,
637 			    CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange));
638 
639 	rcsi2_write(priv, PHYCNT_REG, phycnt);
640 	rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN |
641 		    LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP);
642 	rcsi2_write(priv, FLD_REG, fld);
643 	rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ);
644 	rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ);
645 
646 	ret = rcsi2_wait_phy_start(priv, lanes);
647 	if (ret)
648 		return ret;
649 
650 	/* Run post PHY start initialization, if needed. */
651 	if (priv->info->phy_post_init) {
652 		ret = priv->info->phy_post_init(priv);
653 		if (ret)
654 			return ret;
655 	}
656 
657 	/* Clear Ultra Low Power interrupt. */
658 	if (priv->info->clear_ulps)
659 		rcsi2_write(priv, INTSTATE_REG,
660 			    INTSTATE_INT_ULPS_START |
661 			    INTSTATE_INT_ULPS_END);
662 	return 0;
663 }
664 
rcsi2_start(struct rcar_csi2 * priv)665 static int rcsi2_start(struct rcar_csi2 *priv)
666 {
667 	int ret;
668 
669 	ret = rcsi2_exit_standby(priv);
670 	if (ret < 0)
671 		return ret;
672 
673 	ret = rcsi2_start_receiver(priv);
674 	if (ret) {
675 		rcsi2_enter_standby(priv);
676 		return ret;
677 	}
678 
679 	ret = v4l2_subdev_call(priv->remote, video, s_stream, 1);
680 	if (ret) {
681 		rcsi2_enter_standby(priv);
682 		return ret;
683 	}
684 
685 	return 0;
686 }
687 
rcsi2_stop(struct rcar_csi2 * priv)688 static void rcsi2_stop(struct rcar_csi2 *priv)
689 {
690 	rcsi2_enter_standby(priv);
691 	v4l2_subdev_call(priv->remote, video, s_stream, 0);
692 }
693 
rcsi2_s_stream(struct v4l2_subdev * sd,int enable)694 static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable)
695 {
696 	struct rcar_csi2 *priv = sd_to_csi2(sd);
697 	int ret = 0;
698 
699 	mutex_lock(&priv->lock);
700 
701 	if (!priv->remote) {
702 		ret = -ENODEV;
703 		goto out;
704 	}
705 
706 	if (enable && priv->stream_count == 0) {
707 		ret = rcsi2_start(priv);
708 		if (ret)
709 			goto out;
710 	} else if (!enable && priv->stream_count == 1) {
711 		rcsi2_stop(priv);
712 	}
713 
714 	priv->stream_count += enable ? 1 : -1;
715 out:
716 	mutex_unlock(&priv->lock);
717 
718 	return ret;
719 }
720 
rcsi2_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)721 static int rcsi2_set_pad_format(struct v4l2_subdev *sd,
722 				struct v4l2_subdev_state *sd_state,
723 				struct v4l2_subdev_format *format)
724 {
725 	struct rcar_csi2 *priv = sd_to_csi2(sd);
726 	struct v4l2_mbus_framefmt *framefmt;
727 
728 	if (!rcsi2_code_to_fmt(format->format.code))
729 		format->format.code = rcar_csi2_formats[0].code;
730 
731 	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
732 		priv->mf = format->format;
733 	} else {
734 		framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
735 		*framefmt = format->format;
736 	}
737 
738 	return 0;
739 }
740 
rcsi2_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)741 static int rcsi2_get_pad_format(struct v4l2_subdev *sd,
742 				struct v4l2_subdev_state *sd_state,
743 				struct v4l2_subdev_format *format)
744 {
745 	struct rcar_csi2 *priv = sd_to_csi2(sd);
746 
747 	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
748 		format->format = priv->mf;
749 	else
750 		format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0);
751 
752 	return 0;
753 }
754 
755 static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = {
756 	.s_stream = rcsi2_s_stream,
757 };
758 
759 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = {
760 	.set_fmt = rcsi2_set_pad_format,
761 	.get_fmt = rcsi2_get_pad_format,
762 };
763 
764 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = {
765 	.video	= &rcar_csi2_video_ops,
766 	.pad	= &rcar_csi2_pad_ops,
767 };
768 
rcsi2_irq(int irq,void * data)769 static irqreturn_t rcsi2_irq(int irq, void *data)
770 {
771 	struct rcar_csi2 *priv = data;
772 	u32 status, err_status;
773 
774 	status = rcsi2_read(priv, INTSTATE_REG);
775 	err_status = rcsi2_read(priv, INTERRSTATE_REG);
776 
777 	if (!status)
778 		return IRQ_HANDLED;
779 
780 	rcsi2_write(priv, INTSTATE_REG, status);
781 
782 	if (!err_status)
783 		return IRQ_HANDLED;
784 
785 	rcsi2_write(priv, INTERRSTATE_REG, err_status);
786 
787 	dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n");
788 
789 	return IRQ_WAKE_THREAD;
790 }
791 
rcsi2_irq_thread(int irq,void * data)792 static irqreturn_t rcsi2_irq_thread(int irq, void *data)
793 {
794 	struct rcar_csi2 *priv = data;
795 
796 	mutex_lock(&priv->lock);
797 	rcsi2_stop(priv);
798 	usleep_range(1000, 2000);
799 	if (rcsi2_start(priv))
800 		dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n");
801 	mutex_unlock(&priv->lock);
802 
803 	return IRQ_HANDLED;
804 }
805 
806 /* -----------------------------------------------------------------------------
807  * Async handling and registration of subdevices and links.
808  */
809 
rcsi2_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)810 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier,
811 			      struct v4l2_subdev *subdev,
812 			      struct v4l2_async_subdev *asd)
813 {
814 	struct rcar_csi2 *priv = notifier_to_csi2(notifier);
815 	int pad;
816 
817 	pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode,
818 					  MEDIA_PAD_FL_SOURCE);
819 	if (pad < 0) {
820 		dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name);
821 		return pad;
822 	}
823 
824 	priv->remote = subdev;
825 	priv->remote_pad = pad;
826 
827 	dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad);
828 
829 	return media_create_pad_link(&subdev->entity, pad,
830 				     &priv->subdev.entity, 0,
831 				     MEDIA_LNK_FL_ENABLED |
832 				     MEDIA_LNK_FL_IMMUTABLE);
833 }
834 
rcsi2_notify_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)835 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier,
836 				struct v4l2_subdev *subdev,
837 				struct v4l2_async_subdev *asd)
838 {
839 	struct rcar_csi2 *priv = notifier_to_csi2(notifier);
840 
841 	priv->remote = NULL;
842 
843 	dev_dbg(priv->dev, "Unbind %s\n", subdev->name);
844 }
845 
846 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = {
847 	.bound = rcsi2_notify_bound,
848 	.unbind = rcsi2_notify_unbind,
849 };
850 
rcsi2_parse_v4l2(struct rcar_csi2 * priv,struct v4l2_fwnode_endpoint * vep)851 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,
852 			    struct v4l2_fwnode_endpoint *vep)
853 {
854 	unsigned int i;
855 
856 	/* Only port 0 endpoint 0 is valid. */
857 	if (vep->base.port || vep->base.id)
858 		return -ENOTCONN;
859 
860 	if (vep->bus_type != V4L2_MBUS_CSI2_DPHY) {
861 		dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type);
862 		return -EINVAL;
863 	}
864 
865 	priv->lanes = vep->bus.mipi_csi2.num_data_lanes;
866 	if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) {
867 		dev_err(priv->dev, "Unsupported number of data-lanes: %u\n",
868 			priv->lanes);
869 		return -EINVAL;
870 	}
871 
872 	for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) {
873 		priv->lane_swap[i] = i < priv->lanes ?
874 			vep->bus.mipi_csi2.data_lanes[i] : i;
875 
876 		/* Check for valid lane number. */
877 		if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) {
878 			dev_err(priv->dev, "data-lanes must be in 1-4 range\n");
879 			return -EINVAL;
880 		}
881 	}
882 
883 	return 0;
884 }
885 
rcsi2_parse_dt(struct rcar_csi2 * priv)886 static int rcsi2_parse_dt(struct rcar_csi2 *priv)
887 {
888 	struct v4l2_async_subdev *asd;
889 	struct fwnode_handle *fwnode;
890 	struct fwnode_handle *ep;
891 	struct v4l2_fwnode_endpoint v4l2_ep = {
892 		.bus_type = V4L2_MBUS_CSI2_DPHY
893 	};
894 	int ret;
895 
896 	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0);
897 	if (!ep) {
898 		dev_err(priv->dev, "Not connected to subdevice\n");
899 		return -EINVAL;
900 	}
901 
902 	ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
903 	if (ret) {
904 		dev_err(priv->dev, "Could not parse v4l2 endpoint\n");
905 		fwnode_handle_put(ep);
906 		return -EINVAL;
907 	}
908 
909 	ret = rcsi2_parse_v4l2(priv, &v4l2_ep);
910 	if (ret) {
911 		fwnode_handle_put(ep);
912 		return ret;
913 	}
914 
915 	fwnode = fwnode_graph_get_remote_endpoint(ep);
916 	fwnode_handle_put(ep);
917 
918 	dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode));
919 
920 	v4l2_async_notifier_init(&priv->notifier);
921 	priv->notifier.ops = &rcar_csi2_notify_ops;
922 
923 	asd = v4l2_async_notifier_add_fwnode_subdev(&priv->notifier, fwnode,
924 						    struct v4l2_async_subdev);
925 	fwnode_handle_put(fwnode);
926 	if (IS_ERR(asd))
927 		return PTR_ERR(asd);
928 
929 	ret = v4l2_async_subdev_notifier_register(&priv->subdev,
930 						  &priv->notifier);
931 	if (ret)
932 		v4l2_async_notifier_cleanup(&priv->notifier);
933 
934 	return ret;
935 }
936 
937 /* -----------------------------------------------------------------------------
938  * PHTW initialization sequences.
939  *
940  * NOTE: Magic values are from the datasheet and lack documentation.
941  */
942 
rcsi2_phtw_write(struct rcar_csi2 * priv,u16 data,u16 code)943 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code)
944 {
945 	unsigned int timeout;
946 
947 	rcsi2_write(priv, PHTW_REG,
948 		    PHTW_DWEN | PHTW_TESTDIN_DATA(data) |
949 		    PHTW_CWEN | PHTW_TESTDIN_CODE(code));
950 
951 	/* Wait for DWEN and CWEN to be cleared by hardware. */
952 	for (timeout = 0; timeout <= 20; timeout++) {
953 		if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN)))
954 			return 0;
955 
956 		usleep_range(1000, 2000);
957 	}
958 
959 	dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n");
960 
961 	return -ETIMEDOUT;
962 }
963 
rcsi2_phtw_write_array(struct rcar_csi2 * priv,const struct phtw_value * values)964 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv,
965 				  const struct phtw_value *values)
966 {
967 	const struct phtw_value *value;
968 	int ret;
969 
970 	for (value = values; value->data || value->code; value++) {
971 		ret = rcsi2_phtw_write(priv, value->data, value->code);
972 		if (ret)
973 			return ret;
974 	}
975 
976 	return 0;
977 }
978 
rcsi2_phtw_write_mbps(struct rcar_csi2 * priv,unsigned int mbps,const struct rcsi2_mbps_reg * values,u16 code)979 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps,
980 				 const struct rcsi2_mbps_reg *values, u16 code)
981 {
982 	const struct rcsi2_mbps_reg *value;
983 
984 	for (value = values; value->mbps; value++)
985 		if (value->mbps >= mbps)
986 			break;
987 
988 	if (!value->mbps) {
989 		dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
990 		return -ERANGE;
991 	}
992 
993 	return rcsi2_phtw_write(priv, value->reg, code);
994 }
995 
__rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 * priv,unsigned int mbps)996 static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv,
997 					unsigned int mbps)
998 {
999 	static const struct phtw_value step1[] = {
1000 		{ .data = 0xcc, .code = 0xe2 },
1001 		{ .data = 0x01, .code = 0xe3 },
1002 		{ .data = 0x11, .code = 0xe4 },
1003 		{ .data = 0x01, .code = 0xe5 },
1004 		{ .data = 0x10, .code = 0x04 },
1005 		{ /* sentinel */ },
1006 	};
1007 
1008 	static const struct phtw_value step2[] = {
1009 		{ .data = 0x38, .code = 0x08 },
1010 		{ .data = 0x01, .code = 0x00 },
1011 		{ .data = 0x4b, .code = 0xac },
1012 		{ .data = 0x03, .code = 0x00 },
1013 		{ .data = 0x80, .code = 0x07 },
1014 		{ /* sentinel */ },
1015 	};
1016 
1017 	int ret;
1018 
1019 	ret = rcsi2_phtw_write_array(priv, step1);
1020 	if (ret)
1021 		return ret;
1022 
1023 	if (mbps != 0 && mbps <= 250) {
1024 		ret = rcsi2_phtw_write(priv, 0x39, 0x05);
1025 		if (ret)
1026 			return ret;
1027 
1028 		ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n,
1029 					    0xf1);
1030 		if (ret)
1031 			return ret;
1032 	}
1033 
1034 	return rcsi2_phtw_write_array(priv, step2);
1035 }
1036 
rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 * priv,unsigned int mbps)1037 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps)
1038 {
1039 	return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps);
1040 }
1041 
rcsi2_init_phtw_h3es2(struct rcar_csi2 * priv,unsigned int mbps)1042 static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps)
1043 {
1044 	return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0);
1045 }
1046 
rcsi2_init_phtw_v3m_e3(struct rcar_csi2 * priv,unsigned int mbps)1047 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps)
1048 {
1049 	return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44);
1050 }
1051 
rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 * priv)1052 static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv)
1053 {
1054 	static const struct phtw_value step1[] = {
1055 		{ .data = 0xee, .code = 0x34 },
1056 		{ .data = 0xee, .code = 0x44 },
1057 		{ .data = 0xee, .code = 0x54 },
1058 		{ .data = 0xee, .code = 0x84 },
1059 		{ .data = 0xee, .code = 0x94 },
1060 		{ /* sentinel */ },
1061 	};
1062 
1063 	return rcsi2_phtw_write_array(priv, step1);
1064 }
1065 
1066 /* -----------------------------------------------------------------------------
1067  * Platform Device Driver.
1068  */
1069 
1070 static const struct media_entity_operations rcar_csi2_entity_ops = {
1071 	.link_validate = v4l2_subdev_link_validate,
1072 };
1073 
rcsi2_probe_resources(struct rcar_csi2 * priv,struct platform_device * pdev)1074 static int rcsi2_probe_resources(struct rcar_csi2 *priv,
1075 				 struct platform_device *pdev)
1076 {
1077 	struct resource *res;
1078 	int irq, ret;
1079 
1080 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1081 	priv->base = devm_ioremap_resource(&pdev->dev, res);
1082 	if (IS_ERR(priv->base))
1083 		return PTR_ERR(priv->base);
1084 
1085 	irq = platform_get_irq(pdev, 0);
1086 	if (irq < 0)
1087 		return irq;
1088 
1089 	ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq,
1090 					rcsi2_irq_thread, IRQF_SHARED,
1091 					KBUILD_MODNAME, priv);
1092 	if (ret)
1093 		return ret;
1094 
1095 	priv->rstc = devm_reset_control_get(&pdev->dev, NULL);
1096 
1097 	return PTR_ERR_OR_ZERO(priv->rstc);
1098 }
1099 
1100 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = {
1101 	.init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1102 	.hsfreqrange = hsfreqrange_h3_v3h_m3n,
1103 	.csi0clkfreqrange = 0x20,
1104 	.num_channels = 4,
1105 	.clear_ulps = true,
1106 };
1107 
1108 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es1 = {
1109 	.hsfreqrange = hsfreqrange_m3w_h3es1,
1110 	.num_channels = 4,
1111 };
1112 
1113 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = {
1114 	.init_phtw = rcsi2_init_phtw_h3es2,
1115 	.hsfreqrange = hsfreqrange_h3_v3h_m3n,
1116 	.csi0clkfreqrange = 0x20,
1117 	.num_channels = 4,
1118 	.clear_ulps = true,
1119 };
1120 
1121 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = {
1122 	.hsfreqrange = hsfreqrange_m3w_h3es1,
1123 	.num_channels = 4,
1124 };
1125 
1126 static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = {
1127 	.hsfreqrange = hsfreqrange_m3w_h3es1,
1128 	.num_channels = 4,
1129 };
1130 
1131 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = {
1132 	.init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1133 	.hsfreqrange = hsfreqrange_h3_v3h_m3n,
1134 	.csi0clkfreqrange = 0x20,
1135 	.num_channels = 4,
1136 	.clear_ulps = true,
1137 };
1138 
1139 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = {
1140 	.init_phtw = rcsi2_init_phtw_v3m_e3,
1141 	.phy_post_init = rcsi2_phy_post_init_v3m_e3,
1142 	.num_channels = 4,
1143 };
1144 
1145 static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = {
1146 	.init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1147 	.hsfreqrange = hsfreqrange_h3_v3h_m3n,
1148 	.csi0clkfreqrange = 0x20,
1149 	.clear_ulps = true,
1150 };
1151 
1152 static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = {
1153 	.init_phtw = rcsi2_init_phtw_v3m_e3,
1154 	.phy_post_init = rcsi2_phy_post_init_v3m_e3,
1155 	.num_channels = 2,
1156 };
1157 
1158 static const struct of_device_id rcar_csi2_of_table[] = {
1159 	{
1160 		.compatible = "renesas,r8a774a1-csi2",
1161 		.data = &rcar_csi2_info_r8a7796,
1162 	},
1163 	{
1164 		.compatible = "renesas,r8a774b1-csi2",
1165 		.data = &rcar_csi2_info_r8a77965,
1166 	},
1167 	{
1168 		.compatible = "renesas,r8a774c0-csi2",
1169 		.data = &rcar_csi2_info_r8a77990,
1170 	},
1171 	{
1172 		.compatible = "renesas,r8a774e1-csi2",
1173 		.data = &rcar_csi2_info_r8a7795,
1174 	},
1175 	{
1176 		.compatible = "renesas,r8a7795-csi2",
1177 		.data = &rcar_csi2_info_r8a7795,
1178 	},
1179 	{
1180 		.compatible = "renesas,r8a7796-csi2",
1181 		.data = &rcar_csi2_info_r8a7796,
1182 	},
1183 	{
1184 		.compatible = "renesas,r8a77961-csi2",
1185 		.data = &rcar_csi2_info_r8a77961,
1186 	},
1187 	{
1188 		.compatible = "renesas,r8a77965-csi2",
1189 		.data = &rcar_csi2_info_r8a77965,
1190 	},
1191 	{
1192 		.compatible = "renesas,r8a77970-csi2",
1193 		.data = &rcar_csi2_info_r8a77970,
1194 	},
1195 	{
1196 		.compatible = "renesas,r8a77980-csi2",
1197 		.data = &rcar_csi2_info_r8a77980,
1198 	},
1199 	{
1200 		.compatible = "renesas,r8a77990-csi2",
1201 		.data = &rcar_csi2_info_r8a77990,
1202 	},
1203 	{ /* sentinel */ },
1204 };
1205 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table);
1206 
1207 static const struct soc_device_attribute r8a7795[] = {
1208 	{
1209 		.soc_id = "r8a7795", .revision = "ES1.*",
1210 		.data = &rcar_csi2_info_r8a7795es1,
1211 	},
1212 	{
1213 		.soc_id = "r8a7795", .revision = "ES2.*",
1214 		.data = &rcar_csi2_info_r8a7795es2,
1215 	},
1216 	{ /* sentinel */ },
1217 };
1218 
rcsi2_probe(struct platform_device * pdev)1219 static int rcsi2_probe(struct platform_device *pdev)
1220 {
1221 	const struct soc_device_attribute *attr;
1222 	struct rcar_csi2 *priv;
1223 	unsigned int i;
1224 	int ret;
1225 
1226 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1227 	if (!priv)
1228 		return -ENOMEM;
1229 
1230 	priv->info = of_device_get_match_data(&pdev->dev);
1231 
1232 	/*
1233 	 * The different ES versions of r8a7795 (H3) behave differently but
1234 	 * share the same compatible string.
1235 	 */
1236 	attr = soc_device_match(r8a7795);
1237 	if (attr)
1238 		priv->info = attr->data;
1239 
1240 	priv->dev = &pdev->dev;
1241 
1242 	mutex_init(&priv->lock);
1243 	priv->stream_count = 0;
1244 
1245 	ret = rcsi2_probe_resources(priv, pdev);
1246 	if (ret) {
1247 		dev_err(priv->dev, "Failed to get resources\n");
1248 		return ret;
1249 	}
1250 
1251 	platform_set_drvdata(pdev, priv);
1252 
1253 	ret = rcsi2_parse_dt(priv);
1254 	if (ret)
1255 		return ret;
1256 
1257 	priv->subdev.owner = THIS_MODULE;
1258 	priv->subdev.dev = &pdev->dev;
1259 	v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops);
1260 	v4l2_set_subdevdata(&priv->subdev, &pdev->dev);
1261 	snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s",
1262 		 KBUILD_MODNAME, dev_name(&pdev->dev));
1263 	priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1264 
1265 	priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1266 	priv->subdev.entity.ops = &rcar_csi2_entity_ops;
1267 
1268 	priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
1269 	for (i = RCAR_CSI2_SOURCE_VC0; i < NR_OF_RCAR_CSI2_PAD; i++)
1270 		priv->pads[i].flags = MEDIA_PAD_FL_SOURCE;
1271 
1272 	ret = media_entity_pads_init(&priv->subdev.entity, NR_OF_RCAR_CSI2_PAD,
1273 				     priv->pads);
1274 	if (ret)
1275 		goto error;
1276 
1277 	pm_runtime_enable(&pdev->dev);
1278 
1279 	ret = v4l2_async_register_subdev(&priv->subdev);
1280 	if (ret < 0)
1281 		goto error;
1282 
1283 	dev_info(priv->dev, "%d lanes found\n", priv->lanes);
1284 
1285 	return 0;
1286 
1287 error:
1288 	v4l2_async_notifier_unregister(&priv->notifier);
1289 	v4l2_async_notifier_cleanup(&priv->notifier);
1290 
1291 	return ret;
1292 }
1293 
rcsi2_remove(struct platform_device * pdev)1294 static int rcsi2_remove(struct platform_device *pdev)
1295 {
1296 	struct rcar_csi2 *priv = platform_get_drvdata(pdev);
1297 
1298 	v4l2_async_notifier_unregister(&priv->notifier);
1299 	v4l2_async_notifier_cleanup(&priv->notifier);
1300 	v4l2_async_unregister_subdev(&priv->subdev);
1301 
1302 	pm_runtime_disable(&pdev->dev);
1303 
1304 	return 0;
1305 }
1306 
1307 static struct platform_driver rcar_csi2_pdrv = {
1308 	.remove	= rcsi2_remove,
1309 	.probe	= rcsi2_probe,
1310 	.driver	= {
1311 		.name	= "rcar-csi2",
1312 		.of_match_table	= rcar_csi2_of_table,
1313 	},
1314 };
1315 
1316 module_platform_driver(rcar_csi2_pdrv);
1317 
1318 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>");
1319 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver");
1320 MODULE_LICENSE("GPL");
1321