Searched refs:PPCLK_VCLK_0 (Results 1 – 3 of 3) sorted by relevance
159 CLK_MAP(VCLK, PPCLK_VCLK_0),549 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : in sienna_cichlid_get_smu_metrics_data()550 metrics->CurrClock[PPCLK_VCLK_0]; in sienna_cichlid_get_smu_metrics_data()758 !table_member[PPCLK_VCLK_0].SnapToDiscrete; in sienna_cichlid_set_default_dpm_table()984 case PPCLK_VCLK_0: in sienna_cichlid_get_current_clk_freq_by_table()2416 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, in beige_goby_dump_pptable()2417 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, in beige_goby_dump_pptable()2418 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, in beige_goby_dump_pptable()2419 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, in beige_goby_dump_pptable()2420 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, in beige_goby_dump_pptable()[all …]
39 PPCLK_VCLK_0, enumerator
462 PPCLK_VCLK_0, enumerator
