Searched refs:PPCLK_DCLK_0 (Results 1 – 3 of 3) sorted by relevance
157 CLK_MAP(DCLK, PPCLK_DCLK_0),557 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : in sienna_cichlid_get_smu_metrics_data()558 metrics->CurrClock[PPCLK_DCLK_0]; in sienna_cichlid_get_smu_metrics_data()797 !table_member[PPCLK_DCLK_0].SnapToDiscrete; in sienna_cichlid_set_default_dpm_table()990 case PPCLK_DCLK_0: in sienna_cichlid_get_current_clk_freq_by_table()2395 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, in beige_goby_dump_pptable()2396 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, in beige_goby_dump_pptable()2397 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, in beige_goby_dump_pptable()2398 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, in beige_goby_dump_pptable()2399 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, in beige_goby_dump_pptable()[all …]
38 PPCLK_DCLK_0, enumerator
461 PPCLK_DCLK_0, enumerator
