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Searched refs:PLL1_REFCLK (Results 1 – 2 of 2) sorted by relevance

/Linux-v5.15/drivers/phy/cadence/
Dphy-cadence-sierra.c160 PLL1_REFCLK, enumerator
214 [CMN_PLLLC] = { PLL0_REFCLK, PLL1_REFCLK },
215 [CMN_PLLLC1] = { PLL1_REFCLK, PLL0_REFCLK },
766 sp->input_clks[PLL1_REFCLK] = clk; in cdns_sierra_phy_get_clocks()
/Linux-v5.15/drivers/phy/ti/
Dphy-j721e-wiz.c53 PLL1_REFCLK, enumerator
464 wiz->mux_sel_field[PLL1_REFCLK] = in wiz_regfield_init()
466 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { in wiz_regfield_init()
468 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); in wiz_regfield_init()