Home
last modified time | relevance | path

Searched refs:PHY_SetBBReg (Results 1 – 17 of 17) sorted by relevance

/Linux-v5.15/drivers/staging/rtl8723bs/hal/
DHalPhyRf_8723B.c77 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, value32); in setIqkMatrix_8723B()
80 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32); in setIqkMatrix_8723B()
83 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, value32); in setIqkMatrix_8723B()
90 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); in setIqkMatrix_8723B()
93 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32); in setIqkMatrix_8723B()
96 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, value32); in setIqkMatrix_8723B()
105 …PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); in setIqkMatrix_8723B()
106 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); in setIqkMatrix_8723B()
107 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, 0x00); in setIqkMatrix_8723B()
111 …PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); in setIqkMatrix_8723B()
[all …]
Dodm_DynamicBBPowerSaving.c65 PHY_SetBBReg(pDM_Odm->Adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ in ODM_RF_Saving()
66 PHY_SetBBReg(pDM_Odm->Adapter, 0xc70, BIT3, 0); /* RegC70[3]= 1'b0 */ in ODM_RF_Saving()
67 PHY_SetBBReg(pDM_Odm->Adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]= 0x63 */ in ODM_RF_Saving()
68 PHY_SetBBReg(pDM_Odm->Adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ in ODM_RF_Saving()
69 PHY_SetBBReg(pDM_Odm->Adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]= 0x3 */ in ODM_RF_Saving()
70 PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x0); /* Reg818[28]= 1'b0 */ in ODM_RF_Saving()
71 PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x1); /* Reg818[28]= 1'b1 */ in ODM_RF_Saving()
73 PHY_SetBBReg(pDM_Odm->Adapter, 0x874, 0x1CC000, pDM_PSTable->Reg874); in ODM_RF_Saving()
74 PHY_SetBBReg(pDM_Odm->Adapter, 0xc70, BIT3, pDM_PSTable->RegC70); in ODM_RF_Saving()
75 PHY_SetBBReg(pDM_Odm->Adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); in ODM_RF_Saving()
[all …]
Drtl8723b_phycfg.c115 …PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge… in phy_RFSerialRead_8723B()
119 …PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge… in phy_RFSerialRead_8723B()
123 …PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEd… in phy_RFSerialRead_8723B()
124 …PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge… in phy_RFSerialRead_8723B()
211 PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); in phy_RFSerialWrite_8723B()
415 PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6))); in PHY_BBConfig8723B()
459 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex); in PHY_SetTxPowerIndex()
462 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex); in PHY_SetTxPowerIndex()
465 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex); in PHY_SetTxPowerIndex()
468 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex); in PHY_SetTxPowerIndex()
[all …]
Drtl8723b_rf6052.c108 PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1); in phy_RF6052_Config_ParaFile()
112 PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); in phy_RF6052_Config_ParaFile()
116 …PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 825… in phy_RF6052_Config_ParaFile()
119 …PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255… in phy_RF6052_Config_ParaFile()
134 PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); in phy_RF6052_Config_ParaFile()
137 PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16, u4RegValue); in phy_RF6052_Config_ParaFile()
Dodm_DIG.c21 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); /* 0xe28[7:0]= 0xff th_… in odm_NHMCounterStatisticsInit()
22 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 … in odm_NHMCounterStatisticsInit()
23 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); /* 0xc0c[7]= 1 max power a… in odm_NHMCounterStatisticsInit()
51 PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0); in odm_NHMCounterStatisticsReset()
52 PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1); in odm_NHMCounterStatisticsReset()
137 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskByte0, (u8)TH_L2H_dmc); in odm_SearchPwdBLowerBound()
138 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskByte2, (u8)TH_H2L_dmc); in odm_SearchPwdBLowerBound()
160 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskByte0, (u8)TH_L2H_dmc); in odm_SearchPwdBLowerBound()
161 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskByte2, (u8)TH_H2L_dmc); in odm_SearchPwdBLowerBound()
212 PHY_SetBBReg(pDM_Odm->Adapter, REG_RD_CTRL, BIT11, 1); /* stop counting if EDCCA is asserted */ in odm_AdaptivityInit()
[all …]
Dodm_RegConfig8723B.c113 PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data); in odm_ConfigBB_AGC_8723B()
153 PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data); in odm_ConfigBB_PHY_8723B()
Dodm_NoiseMonitor.c58 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 1); in odm_InbandNoise_Monitor_NSeries()
68 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 0); in odm_InbandNoise_Monitor_NSeries()
Dodm_CfoTracking.c22 PHY_SetBBReg( in odm_SetCrystalCap()
48 PHY_SetBBReg( in odm_SetATCStatus()
Dhal_btcoex.c687 PHY_SetBBReg(padapter, RegAddr, BitMask, Data); in halbtcoutsrc_SetBbReg()
/Linux-v5.15/drivers/staging/r8188eu/hal/
Drtl8188e_mp.c403 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0); in Hal_SetAntenna()
404 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT(26), 1); in Hal_SetAntenna()
405 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT(10), 0); in Hal_SetAntenna()
406 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT(1), 1); in Hal_SetAntenna()
407 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT(17), 0); in Hal_SetAntenna()
419 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); in Hal_SetAntenna()
420 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); in Hal_SetAntenna()
428 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT(10), 1); in Hal_SetAntenna()
429 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT(10), 0); in Hal_SetAntenna()
430 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0); in Hal_SetAntenna()
[all …]
Drtl8188e_rf6052.c210 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); in rtl8188e_PHY_RF6052SetCckTxPower()
212 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); in rtl8188e_PHY_RF6052SetCckTxPower()
216 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); in rtl8188e_PHY_RF6052SetCckTxPower()
218 PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); in rtl8188e_PHY_RF6052SetCckTxPower()
375 PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal); in writeOFDMPowerReg88E()
482 PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1); in phy_RF6052_Config_ParaFile()
486 PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); in phy_RF6052_Config_ParaFile()
490 …PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 825… in phy_RF6052_Config_ParaFile()
493 …PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255… in phy_RF6052_Config_ParaFile()
515 PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); in phy_RF6052_Config_ParaFile()
[all …]
Drtl8188e_phycfg.c172 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong & (~bLSSIReadEdge)); in phy_RFSerialRead()
175 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); in phy_RFSerialRead()
266 PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); in phy_RFSerialWrite()
598 PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6))); in PHY_BBConfig8188E()
1004 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); in _PHY_SetBWMode92C()
1005 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); in _PHY_SetBWMode92C()
1009 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); in _PHY_SetBWMode92C()
1010 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); in _PHY_SetBWMode92C()
1012 PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1)); in _PHY_SetBWMode92C()
1013 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); in _PHY_SetBWMode92C()
[all …]
Dodm_interface.c46 PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); in ODM_SetMACReg()
58 PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); in ODM_SetBBReg()
Dusb_halinit.c622 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); in _BBTurnOnBlock()
623 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); in _BBTurnOnBlock()
640 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01); in _InitAntenna_Selection()
/Linux-v5.15/drivers/staging/r8188eu/include/
DHal8188EPhyCfg.h228 #define PHY_SetBBReg(adapt, regaddr, bitmask, data) \ macro
235 #define PHY_SetMacReg PHY_SetBBReg
/Linux-v5.15/drivers/staging/rtl8723bs/include/
Dhal_intf.h335 #define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (Bi… macro
339 #define PHY_SetMacReg PHY_SetBBReg
/Linux-v5.15/drivers/staging/r8188eu/core/
Drtw_mp.c933 PHY_SetBBReg(pAdapter, REG_AFE_XTAL_CTRL, 0x7FF800, in Hal_ProSetCrystalCap()