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Searched refs:OTP (Results 1 – 25 of 26) sorted by relevance

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/Linux-v5.15/drivers/mtd/nand/onenand/
DKconfig43 bool "OneNAND OTP Support"
47 Also, 1st Block of NAND Flash Array can be used as OTP.
49 The OTP block can be read, programmed and locked using the same
51 OTP block cannot be erased.
53 OTP block is fully-guaranteed to be a valid block.
/Linux-v5.15/drivers/nvmem/
DKconfig36 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
40 This is a driver for the On-Chip OTP Controller (OCOTP) available on
48 tristate "i.MX8 SCU On-Chip OTP Controller support"
52 This is a driver for the SCU On-Chip OTP Controller (OCOTP)
78 tristate "NXP LPC18XX OTP Memory Support"
82 Say Y here to include support for NXP LPC18xx OTP memory found on
88 tristate "Freescale MXS On-Chip OTP Memory Support"
111 tristate "Nintendo Wii and Wii U OTP Support"
114 This is a driver exposing the OTP of a Nintendo Wii or Wii U console.
153 tristate "Rockchip OTP controller support"
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/nvmem/
Dvf610-ocotp.txt1 On-Chip OTP Memory for Freescale Vybrid
8 reg : Address and length of OTP controller and fuse map registers
Dlpc1850-otp.txt1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
Dbrcm,ocotp.txt1 Broadcom OTP memory controller
8 - reg: Base address of the OTP controller.
Drockchip-otp.txt1 Rockchip internal OTP (One Time Programmable) memory device tree bindings
/Linux-v5.15/Documentation/devicetree/bindings/regulator/
Dpalmas-pmic.txt3 The tps659038 for the AM57x class have OTP spins that
5 is not a need to add the OTP spins to the palmas driver. The
35 For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
50 ti,smps-range - OTP has the wrong range set for the hardware so override
/Linux-v5.15/Documentation/devicetree/bindings/net/
Dmicrochip,lan78xx.txt3 The LAN78XX devices are usually configured by programming their OTP or with
5 The Device Tree properties, if present, override the OTP and EEPROM.
/Linux-v5.15/Documentation/hwmon/
Dsht15.rst48 The humidity calibration coefficients are programmed into an OTP memory on the
67 flag to indicate not to reload from OTP (default to false).
/Linux-v5.15/Documentation/ABI/testing/
Ddebugfs-turris-mox-rwtm9 device's OTP. The message must be exactly 64 bytes
/Linux-v5.15/drivers/mtd/chips/
DKconfig154 bool "Protection Registers aka one-time programmable (OTP) bits"
164 programmable (OTP) bits; when programmed, register bits cannot be
171 because the Lock Register bits themselves are OTP, when programmed,
176 in the programming of OTP bits will waste them.
/Linux-v5.15/Documentation/devicetree/bindings/mfd/
Dpalmas.txt31 hardware, if not set will use muxing in OTP.
Dda9063.txt18 modified to match the chip's OTP settings).
Dda9062.txt35 modified to match the chip's OTP settings).
/Linux-v5.15/Documentation/w1/slaves/
Dw1_ds2406.rst15 These chips also provide 128 bytes of OTP EPROM, but reading/writing it is
/Linux-v5.15/Documentation/devicetree/bindings/input/
Dti,palmas-pwrbutton.txt18 NOTE: This depends on OTP support and POWERHOLD signal configuration
/Linux-v5.15/arch/arm/boot/dts/
Dberlin2cd-valve-steamlink.dts42 * less depending on leakage value in OTP), and buck2 likely used for
Dimx6q-gk802.dts66 /* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */
/Linux-v5.15/drivers/soc/amlogic/
Dmeson-secure-pwrc.c106 SEC_PD(OTP, 0),
/Linux-v5.15/drivers/mtd/devices/
DKconfig73 bool "DataFlash OTP support (Security Register)"
77 one-time-programmable (OTP) data. The first half may be written
/Linux-v5.15/drivers/ptp/
Didt8a340_reg.h518 #define OTP 0xcf70 macro
/Linux-v5.15/arch/powerpc/boot/dts/
Dwii.dts222 * requires refactoring the PIC1, GPIO and OTP nodes
/Linux-v5.15/include/linux/mfd/
Didt8a340_reg.h448 #define OTP 0xcf70 macro
/Linux-v5.15/arch/arm64/boot/dts/nvidia/
Dtegra210-smaug.dts1384 * set by OTP) and down properly.
/Linux-v5.15/drivers/regulator/
DKconfig836 reading the mux info from OTP.

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