| /Linux-v5.15/drivers/gpu/drm/amd/amdgpu/ |
| D | vega20_reg_init.c | 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
49 adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
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| D | cyan_skillfish_reg_init.c | 39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in cyan_skillfish_reg_base_init()
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| D | vangogh_reg_init.c | 39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vangogh_reg_base_init()
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| D | yellow_carp_reg_init.c | 39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in yellow_carp_reg_base_init()
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| D | navi10_reg_init.c | 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in navi10_reg_base_init()
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| D | dimgrey_cavefish_reg_init.c | 39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
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| D | sienna_cichlid_reg_init.c | 39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in sienna_cichlid_reg_base_init()
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| D | beige_goby_reg_init.c | 39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in beige_goby_reg_base_init()
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| D | aldebaran_reg_init.c | 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in aldebaran_reg_base_init()
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| D | vega10_reg_init.c | 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 131 #define NBIO_BASE(seg) \ macro
494 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
495 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
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| /Linux-v5.15/drivers/gpu/drm/amd/include/ |
| D | cyan_skillfish_ip_offset.h | 99 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x000… variable
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| D | navi10_ip_offset.h | 97 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x000… variable
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| D | vega20_ip_offset.h | 99 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x000… variable
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| D | dimgrey_cavefish_ip_offset.h | 123 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
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| D | sienna_cichlid_ip_offset.h | 130 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
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| D | beige_goby_ip_offset.h | 138 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
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| D | vega10_ip_offset.h | 43 static const struct IP_BASE __maybe_unused NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, … variable
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| D | vangogh_ip_offset.h | 162 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
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| D | yellow_carp_offset.h | 132 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
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| D | aldebaran_ip_offset.h | 147 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 197 #define NBIO_BASE(seg) \ macro
201 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 301 #define NBIO_BASE(seg) \ macro
305 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 278 #define NBIO_BASE(seg) \ macro
282 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 336 #define NBIO_BASE(seg) \ macro
340 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
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