Searched refs:MVPP22_XLG_CTRL0_REG (Results 1 – 2 of 2) sorted by relevance
1767 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()1770 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()1785 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()1787 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()2148 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & in mvpp2_mac_reset_assert()2150 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_reset_assert()5905 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_init()5908 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_init()6127 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_pcs_get_state()6362 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_xlg_config()[all …]
488 #define MVPP22_XLG_CTRL0_REG 0x100 macro
