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Searched refs:MUX_GATE_CLR_SET_UPD (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.15/drivers/clk/mediatek/
Dclk-mt6779.c642 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
644 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
647 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
649 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
651 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
653 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
656 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
658 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
660 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
662 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents,
[all …]
Dclk-mt8192.c714 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",
720 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel",
722 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel",
724 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel",
726 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel",
729 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
731 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel",
733 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
735 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
738 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel",
[all …]
Dclk-mt8183.c528 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
531 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
534 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
538 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
541 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
544 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
547 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
551 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
554 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
557 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel",
[all …]
Dclk-mt6765.c373 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
376 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
380 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1,
383 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1,
386 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
389 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
393 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
396 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg_parents,
399 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
402 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
[all …]
Dclk-mux.h70 #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ macro