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Searched refs:MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h24117 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
Ddcn_2_1_0_sh_mask.h20185 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
Ddcn_3_0_1_sh_mask.h40068 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
Ddcn_3_1_2_sh_mask.h22524 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
Ddcn_3_0_2_sh_mask.h47070 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
Ddcn_2_0_0_sh_mask.h23253 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro
Ddcn_3_0_0_sh_mask.h54220 #define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT … macro