Searched refs:MG_REFCLKIN_CTL_OD_2_MUX_MASK (Results 1 – 2 of 2) sorted by relevance
3361 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; in mg_pll_get_hw_state()3432 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; in dkl_pll_get_hw_state()3597 val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; in icl_mg_pll_write()3650 val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; in dkl_pll_write()
10631 #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8) macro
