1 /*
2 * QorIQ 10G MDIO Controller
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 * Copyright 2021 NXP
6 *
7 * Authors: Andy Fleming <afleming@freescale.com>
8 * Timur Tabi <timur@freescale.com>
9 *
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
13 */
14
15 #include <linux/acpi.h>
16 #include <linux/acpi_mdio.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/mdio.h>
20 #include <linux/module.h>
21 #include <linux/of_address.h>
22 #include <linux/of_mdio.h>
23 #include <linux/of_platform.h>
24 #include <linux/phy.h>
25 #include <linux/slab.h>
26
27 /* Number of microseconds to wait for a register to respond */
28 #define TIMEOUT 1000
29
30 struct tgec_mdio_controller {
31 __be32 reserved[12];
32 __be32 mdio_stat; /* MDIO configuration and status */
33 __be32 mdio_ctl; /* MDIO control */
34 __be32 mdio_data; /* MDIO data */
35 __be32 mdio_addr; /* MDIO address */
36 } __packed;
37
38 #define MDIO_STAT_ENC BIT(6)
39 #define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
40 #define MDIO_STAT_BSY BIT(0)
41 #define MDIO_STAT_RD_ER BIT(1)
42 #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
43 #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
44 #define MDIO_CTL_PRE_DIS BIT(10)
45 #define MDIO_CTL_SCAN_EN BIT(11)
46 #define MDIO_CTL_POST_INC BIT(14)
47 #define MDIO_CTL_READ BIT(15)
48
49 #define MDIO_DATA(x) (x & 0xffff)
50 #define MDIO_DATA_BSY BIT(31)
51
52 struct mdio_fsl_priv {
53 struct tgec_mdio_controller __iomem *mdio_base;
54 bool is_little_endian;
55 bool has_a011043;
56 };
57
xgmac_read32(void __iomem * regs,bool is_little_endian)58 static u32 xgmac_read32(void __iomem *regs,
59 bool is_little_endian)
60 {
61 if (is_little_endian)
62 return ioread32(regs);
63 else
64 return ioread32be(regs);
65 }
66
xgmac_write32(u32 value,void __iomem * regs,bool is_little_endian)67 static void xgmac_write32(u32 value,
68 void __iomem *regs,
69 bool is_little_endian)
70 {
71 if (is_little_endian)
72 iowrite32(value, regs);
73 else
74 iowrite32be(value, regs);
75 }
76
77 /*
78 * Wait until the MDIO bus is free
79 */
xgmac_wait_until_free(struct device * dev,struct tgec_mdio_controller __iomem * regs,bool is_little_endian)80 static int xgmac_wait_until_free(struct device *dev,
81 struct tgec_mdio_controller __iomem *regs,
82 bool is_little_endian)
83 {
84 unsigned int timeout;
85
86 /* Wait till the bus is free */
87 timeout = TIMEOUT;
88 while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
89 MDIO_STAT_BSY) && timeout) {
90 cpu_relax();
91 timeout--;
92 }
93
94 if (!timeout) {
95 dev_err(dev, "timeout waiting for bus to be free\n");
96 return -ETIMEDOUT;
97 }
98
99 return 0;
100 }
101
102 /*
103 * Wait till the MDIO read or write operation is complete
104 */
xgmac_wait_until_done(struct device * dev,struct tgec_mdio_controller __iomem * regs,bool is_little_endian)105 static int xgmac_wait_until_done(struct device *dev,
106 struct tgec_mdio_controller __iomem *regs,
107 bool is_little_endian)
108 {
109 unsigned int timeout;
110
111 /* Wait till the MDIO write is complete */
112 timeout = TIMEOUT;
113 while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
114 MDIO_STAT_BSY) && timeout) {
115 cpu_relax();
116 timeout--;
117 }
118
119 if (!timeout) {
120 dev_err(dev, "timeout waiting for operation to complete\n");
121 return -ETIMEDOUT;
122 }
123
124 return 0;
125 }
126
127 /*
128 * Write value to the PHY for this device to the register at regnum,waiting
129 * until the write is done before it returns. All PHY configuration has to be
130 * done through the TSEC1 MIIM regs.
131 */
xgmac_mdio_write(struct mii_bus * bus,int phy_id,int regnum,u16 value)132 static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
133 {
134 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
135 struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
136 uint16_t dev_addr;
137 u32 mdio_ctl, mdio_stat;
138 int ret;
139 bool endian = priv->is_little_endian;
140
141 mdio_stat = xgmac_read32(®s->mdio_stat, endian);
142 if (regnum & MII_ADDR_C45) {
143 /* Clause 45 (ie 10G) */
144 dev_addr = (regnum >> 16) & 0x1f;
145 mdio_stat |= MDIO_STAT_ENC;
146 } else {
147 /* Clause 22 (ie 1G) */
148 dev_addr = regnum & 0x1f;
149 mdio_stat &= ~MDIO_STAT_ENC;
150 }
151
152 xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
153
154 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
155 if (ret)
156 return ret;
157
158 /* Set the port and dev addr */
159 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
160 xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
161
162 /* Set the register address */
163 if (regnum & MII_ADDR_C45) {
164 xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
165
166 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
167 if (ret)
168 return ret;
169 }
170
171 /* Write the value to the register */
172 xgmac_write32(MDIO_DATA(value), ®s->mdio_data, endian);
173
174 ret = xgmac_wait_until_done(&bus->dev, regs, endian);
175 if (ret)
176 return ret;
177
178 return 0;
179 }
180
181 /*
182 * Reads from register regnum in the PHY for device dev, returning the value.
183 * Clears miimcom first. All PHY configuration has to be done through the
184 * TSEC1 MIIM regs.
185 */
xgmac_mdio_read(struct mii_bus * bus,int phy_id,int regnum)186 static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
187 {
188 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
189 struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
190 uint16_t dev_addr;
191 uint32_t mdio_stat;
192 uint32_t mdio_ctl;
193 uint16_t value;
194 int ret;
195 bool endian = priv->is_little_endian;
196
197 mdio_stat = xgmac_read32(®s->mdio_stat, endian);
198 if (regnum & MII_ADDR_C45) {
199 dev_addr = (regnum >> 16) & 0x1f;
200 mdio_stat |= MDIO_STAT_ENC;
201 } else {
202 dev_addr = regnum & 0x1f;
203 mdio_stat &= ~MDIO_STAT_ENC;
204 }
205
206 xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
207
208 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
209 if (ret)
210 return ret;
211
212 /* Set the Port and Device Addrs */
213 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
214 xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
215
216 /* Set the register address */
217 if (regnum & MII_ADDR_C45) {
218 xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
219
220 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
221 if (ret)
222 return ret;
223 }
224
225 /* Initiate the read */
226 xgmac_write32(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl, endian);
227
228 ret = xgmac_wait_until_done(&bus->dev, regs, endian);
229 if (ret)
230 return ret;
231
232 /* Return all Fs if nothing was there */
233 if ((xgmac_read32(®s->mdio_stat, endian) & MDIO_STAT_RD_ER) &&
234 !priv->has_a011043) {
235 dev_dbg(&bus->dev,
236 "Error while reading PHY%d reg at %d.%hhu\n",
237 phy_id, dev_addr, regnum);
238 return 0xffff;
239 }
240
241 value = xgmac_read32(®s->mdio_data, endian) & 0xffff;
242 dev_dbg(&bus->dev, "read %04x\n", value);
243
244 return value;
245 }
246
xgmac_mdio_probe(struct platform_device * pdev)247 static int xgmac_mdio_probe(struct platform_device *pdev)
248 {
249 struct fwnode_handle *fwnode;
250 struct mdio_fsl_priv *priv;
251 struct resource *res;
252 struct mii_bus *bus;
253 int ret;
254
255 /* In DPAA-1, MDIO is one of the many FMan sub-devices. The FMan
256 * defines a register space that spans a large area, covering all the
257 * subdevice areas. Therefore, MDIO cannot claim exclusive access to
258 * this register area.
259 */
260 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
261 if (!res) {
262 dev_err(&pdev->dev, "could not obtain address\n");
263 return -EINVAL;
264 }
265
266 bus = mdiobus_alloc_size(sizeof(struct mdio_fsl_priv));
267 if (!bus)
268 return -ENOMEM;
269
270 bus->name = "Freescale XGMAC MDIO Bus";
271 bus->read = xgmac_mdio_read;
272 bus->write = xgmac_mdio_write;
273 bus->parent = &pdev->dev;
274 bus->probe_capabilities = MDIOBUS_C22_C45;
275 snprintf(bus->id, MII_BUS_ID_SIZE, "%pa", &res->start);
276
277 /* Set the PHY base address */
278 priv = bus->priv;
279 priv->mdio_base = ioremap(res->start, resource_size(res));
280 if (!priv->mdio_base) {
281 ret = -ENOMEM;
282 goto err_ioremap;
283 }
284
285 /* For both ACPI and DT cases, endianness of MDIO controller
286 * needs to be specified using "little-endian" property.
287 */
288 priv->is_little_endian = device_property_read_bool(&pdev->dev,
289 "little-endian");
290
291 priv->has_a011043 = device_property_read_bool(&pdev->dev,
292 "fsl,erratum-a011043");
293
294 fwnode = pdev->dev.fwnode;
295 if (is_of_node(fwnode))
296 ret = of_mdiobus_register(bus, to_of_node(fwnode));
297 else if (is_acpi_node(fwnode))
298 ret = acpi_mdiobus_register(bus, fwnode);
299 else
300 ret = -EINVAL;
301 if (ret) {
302 dev_err(&pdev->dev, "cannot register MDIO bus\n");
303 goto err_registration;
304 }
305
306 platform_set_drvdata(pdev, bus);
307
308 return 0;
309
310 err_registration:
311 iounmap(priv->mdio_base);
312
313 err_ioremap:
314 mdiobus_free(bus);
315
316 return ret;
317 }
318
xgmac_mdio_remove(struct platform_device * pdev)319 static int xgmac_mdio_remove(struct platform_device *pdev)
320 {
321 struct mii_bus *bus = platform_get_drvdata(pdev);
322
323 mdiobus_unregister(bus);
324 iounmap(bus->priv);
325 mdiobus_free(bus);
326
327 return 0;
328 }
329
330 static const struct of_device_id xgmac_mdio_match[] = {
331 {
332 .compatible = "fsl,fman-xmdio",
333 },
334 {
335 .compatible = "fsl,fman-memac-mdio",
336 },
337 {},
338 };
339 MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
340
341 static const struct acpi_device_id xgmac_acpi_match[] = {
342 { "NXP0006" },
343 { }
344 };
345 MODULE_DEVICE_TABLE(acpi, xgmac_acpi_match);
346
347 static struct platform_driver xgmac_mdio_driver = {
348 .driver = {
349 .name = "fsl-fman_xmdio",
350 .of_match_table = xgmac_mdio_match,
351 .acpi_match_table = xgmac_acpi_match,
352 },
353 .probe = xgmac_mdio_probe,
354 .remove = xgmac_mdio_remove,
355 };
356
357 module_platform_driver(xgmac_mdio_driver);
358
359 MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
360 MODULE_LICENSE("GPL v2");
361
